Performance Analysis for Using Non-Volatile Memory DIMMs: Opportunities and Challenges.
Abstract not provided.
Awad, Amro↗
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Messier: A Detailed NVM-Based DIMM Model for the SST Simulation Framework.
DRAM technology is the main building block of main memory, however, DRAM scaling is becoming very challenging. The main issues for DRAM scaling are the increasing error rates with each new generation, the geometric and physical constraints of scaling the capacitor part of the DRAM cells, and the high power consumption caused by the continuous need for refreshing cell values. At the same time, emerging Non- Volatile Memory (NVM) technologies, such as Phase-Change Memory (PCM), are emerging as promising replacements for DRAM. NVMs, when compared to current technologies e.g., NAND-based ash, have latencies comparable to DRAM. Additionally, NVMs are non-volatile, which eliminates the need for refresh power and enables persistent memory applications. Finally, NVMs have promising densities and the potential for multi-level cell (MLC) storage.
97 MATHEMATICS AND COMPUTING↗
Seeing values for LSST strategy simulations
The opsim4 operations simulation program for the LSST astronomical survey uses a database of seeing values covering the range of times to besimulated. Idescribethe creation of such a database using Dual Image Motion Monitor(DIMM)datacollected at Cerro Pachon from 2004-03-17 to 2019-10-07. In times during which the data overlap, I compare the distribution of DIMM seeing values to the seeing measured in DECamimages,takenatasite 10kmaway. Becauseinstrumentalproblemsinthe DIMMmay indicate unreliablemeasurements,cutsonimagequality(asindicatedby the measured Strehlratio)wereexplored. TheDIMMhassignificantgaps,soImodel thedata(withandwithoutcutsonStrehlratio)andgenerateartificialdatainthegaps according to the model. The model consists of a sinusoidal variation with a period of one year, an autoregressive (AR1) model for variations in mean seeing from one night to the next, and another AR1 model for variations on a 5 minute timescale. I create four databases according to thisprocedure, twobasedonDIMMdatastarting 2006-01-01 (with and without a Strehl ratio cut), and two starting 2009-01-01. I then run opsim simulations using each, and an otherwise identical simulation using the default seeing database, and explore the differences
Neilsen, Eric H. [Fermilab]↗
The implementation of Global Feature EXtractor (gFEX) - the ATLAS Calorimeter Level 1 Trigger system for LHC Run-3 upgrade
As part of the ATLAS Phase-I Upgrade, the global Feature EXtractor (gFEX) is one of several hardware modules designed to help maintain the ATLAS Level-1 trigger acceptance rate with the increasing Large Hadron Collider (LHC) luminosity and the increasing Pile-Up conditions. The gFEX is used to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W & Z bosons, top quarks, and exotic particles in real time at the 40 MHz LHC bunch crossing rate. The board is required to receive coarse-granularity (Δη×Δphiv = 0.2×0.2 gTower) information from the entire ATLAS calorimeters on 276 optical fibers. A prototype v1 with one Xilinx ZYNQ FPGA, and one Vertex-7 FPGA for technology validation has been designed and tested in 2015. With the lessons learned from the prototype v1, a prototype v2 with three Vertex UltraScale FPGAs and one ZYNQ FPGA has been implemented to verify full functionalities of gFEX in 2016. Based on the prototype v2 design, a prototype v3, the final gFEX prototype, is implemented, which is an ATCA module consisting of three Vertex UltraScale+ FPGAs, one ZYNQ UltraScale+ SoC, and 35 MiniPODs. This board receives up to 300 fiber optical links from calorimeters and transmits trigger data on 96 links to the to the ATLAS Level-1 Topological trigger (L1Topo [1]) at the speed up to 12.8 Gb/s. There are also 24 electrical links on board for communication between two FPGAs with the speed up to 25.6 Gb/s. The performance of three prototype boards have been tested and evaluated. For the prototype v3 board, the high-speed optical links are stable at 12.8 Gb/s with Bit Error Ratio (BER) < 1 × 10 -15 . The low-latency parallel GPIO (General Purpose I/O) buses between FPGAs are stable at 1.12 Gb/s. The peripheral components of ZYNQ UltraScale+ SoC, such as 16 GB DDR4 DIMM, UART, SPI flashes, and Ethernet, have also been verified. Here, the test results of the prototype v3 board validate the gFEX technologies, architecture and full functionalities. Now the final production board is being produced.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
simsee
Simsee is a program for generating artificial seeing data for simulations of astronomical surveys. It includes a jupyter notebook for deriving model parameters from Dual Image Motion Monitor (DIMM) data, and a program that reads these model parameters and creates a data file suitable for use by survey strategy simulation code (which is outside the scope of this package). It is specifically designed to provide input data for LSST’s opsim4 survey simulator, but may be adapted for use with different simulators as well. The code is verified to work on a Linux workstation with an Intel Xeon E5-6980 CPU and 256GB or memory, but should work fine on systems with far more limited resources.
Neilsen, Eric↗