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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗
DOE OSTI2024

A novel design optimization framework to sustain remanufacturability

The ever-increasing global carbon emissions have urged the need for environmentally conscious/sustainable product design, for which the design for remanufacturing (DfRem) is one potential approach. DfRem targets at designing products that have multiple life cycles, thus significantly reducing raw material usage, energy consumption, and carbon emissions. In this paper, we develop a three-stage framework that consists of (1) systematic design space exploration and a multi-objective optimization formulation to minimize the likelihood of failure causes (such as fatigue and wear) and environmental footprint, (2) topology optimization to further reduce material usage without significantly affecting the load-carrying capability of the product, and (3) post-topology optimization design verification to ensure the proposed design satisfies all design constraints. The environmental impact can be assessed at varying comprehensiveness levels (e.g., design and manufacturing phase, use phase) and in terms of carbon or GHG emission, energy use, and waste generation. Because the novel design framework predominantly adjusted the geometry, we focused on mass-based change and energy savings due to sustained remanufacturability. The multi-objective optimization formulation in the first step results in a Pareto optimal set of possible design solutions that the designer can use for the second step. Finally, we demonstrate the utility of this framework through a case study of an engine cylinder head subjected to thermo-mechanical loads, where we find that about 5% of the product mass can be conserved with only about a 3% increase in surface area that has a fatigue life less than 10,000 cycles.

42 ENGINEERING↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Extended-MHD simulations of disruption mitigation via massive gas injection in SPARC

Recent developments to the M3D-C1 code enable higher fidelity modeling of disruptions, and can be applied in the design verification of reactor-scale tokamaks. Among these new capabilities is a method to mesh conducting vessel structures such as coils and passive plates, packing of the toroidal mesh around gas injectors, as well as anisotropic resistivity inside the vessel structures. We present extended-magnetohydrodynamic (MHD) simulations of disruption mitigation via massive gas injection (MGI) in SPARC. The goal of this study is to inform the disruption mitigation layout of SPARC and aid in the design of an effective gas injector configuration. Fully three-dimensional simulations with M3D-C1 are carried out for various injector configurations with the primary goal of determining the effect of different MGI parameters on heat loads and vessel forces. The simulations include a model for impurity ionization, recombination, advection and radiation, as well as spatially resolved conducting structures around the plasma. A localized mixture of deuterium and neon with a small toroidal and poloidal width is injected in up to six locations. We demonstrate that M3D-C1 can model a rapid shutdown via MGI using narrow and more realistic gas plumes than in previous simulations. As a result of the q = 1 surface in the SPARC baseline case a sawtooth is observed early in the simulations. Despite the sawtooth and the onset of edge MHD instabilities, the impurity distribution remains localized around the injector locations, but enables a radiative shutdown of the plasma. We find that using the maximum of six gas injectors results in a lower peaking factor and leads to a more even distribution of radiation toroidally than using two injectors.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

Steam generator model design parameter sensitivity study for small modular reactor system

Here, this study focuses on design parameter sensitivity studies pertaining to several Once-Through Steam Generator (OTSG) model cases both with and without a riser using python and advanced risk assessment and optimization tool, i.e. Risk Analysis Virtual Environment (RAVEN) developed at Idaho National Laboratory (INL), to support a Small Modular Reactor (SMR) system. The presented Steam Generator (SG) python-based model is a mathematical representation of a steam-generating unit for a Pressurized Water Reactor (PWR)-type SMR system, including fluid flow and heat transfer equations, models, and correlations. Design studies involve changing the model’s input design parameters (e.g., temperature, pressure, mass flow rate) to observe the resulting effects on the output of the system, such as the Heat Transfer Coefficient (HTC), Reynolds number, Nusselt number, and heat transfer performance. Sensitivity studies analyze the degree to which system output and/or desired parameters (e.g., HTC or heat transfer performance) are sensitive to changes in the input parameters. By using RAVEN, detailed design parametric sensitivity studies. Six input parameters—namely, the pressure, temperature, and mass flow rate for the inlet of the primary-side (hot fluid) and secondary-side (cold fluid) of the SG—were randomly perturbed via RAVEN’s Monte Carlo Sampler module, using uniform distributions (i.e., ±1%, ±5% and ±10 % relative changes) for 600 samples. The analysis results give valuable insights into SG system performance, and provide justification for further research and development such as optimized sensor placement, design verification, validation, and optimization.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
DOE OSTI2026

Design and Performance Assessment of Intermediary Coils for Misalignment Tolerance Improvement in Wireless Power Transfer Systems

This paper investigates the use of intermediate coils positioned between the primary and secondary coils in Wireless Power Transfer (WPT) systems for electric vehicle (EV) charging, with the objective of improving power transfer efficiency and robustness under misalignment conditions. An optimized 1 kW power system that operates at 85 kHz is developed and the misalignment performance was analyzed and compared with and without intermediate coils. A preliminary increase in efficiency of 2.3% at a misalignment of 52% of the coil radius is shown to be possible for a passive intermediate coil. An experimental prototype is built for design verification.

Sivka, Gozde [ORNL]↗
DOE OSTI2025

Developing a Nuclear Quality Assurance Compliant Design Methodology for Neutronic Analysis of Xe-100 Design

The primary objective of this work is to develop a design methodology compliant with nuclear quality assurance standards for the Xe-100 neutronic design verification studies. To achieve this, a Monte Carlo model of the Xe-100 reactor was constructed using the exclusion principle, transformation technique, and universe-based level specification following Idaho National Laboratory (INL) NQA level-1 compliant standards and an NQA-1 compliant version of MCNP6. The model encompasses the entire reactor core structures, including the upper plenum, core region, and lower plenum sections, along with all sub-components. The active core section was represented using the spectral regions, each comprising a particular fuel composition and temperature averaged over the considered zone, calculated by X-energy using Very Superior Old Programs (VSOP). Additionally, a component-wise temperature map was implemented into the model, not only for the core region but also for the structural components. Temperature-dependent cross-section libraries, along with thermal scattering law libraries, generated using INL NQA-1 compliant version of NJOY21, were utilized for each isotope in the burnt fuel and the structural materials. Furthermore, the volume of each modeled component was estimated using a stochastic approach with the ray tracing method in MCNP and criticality calculations were performed.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2026

Vision and Development of a Design, Implementation, and Verification Automation (DIVA) Software Platform for DNA Construction

Abstract DNA construction, while a prerequisite to many biological endeavors, is often a time-consuming distraction from an individual’s primary research objectives. We envisioned that with the right software infrastructure and cultural mindset, a single person could execute in parallel the batched DNA construction tasks of an entire research institute, at scales realizing efficiency gains through process and laboratory automation. In pursuit of this vision, we developed the Design, Implementation, and Verification Automation (DIVA) software platform. DIVA’s web interface enables researchers to design DNA constructs (using visual biological computer-aided design tools and biological parts repositories), submit designs for construction to dedicated staff, and track DNA construction as it progresses. DIVA supports the dedicated staff through the DNA construction process and records both successful and unsuccessful attempts toward improving the overall process. The platform is publicly available at public-diva.jbei.org and its open-source code through github.com/JBEI/DIVA.

Plahar, Hector [DOE Agile BioFoundry , , ,; DOE Jo↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗
DOE OSTI2025

Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators using HLS4ML

With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.

Di Guglielmo, Giuseppe [Fermilab]↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2026

Georgetown University – SYSM 5630 Systems Integration Verification and Validation : Todd Noste

At Lawrence Livermore National Laboratory in the National Ignition Facility Optics Group, we use the systems engineering approach for project management and as a design tool. Systems engineering is used in a graded approach to design and project management that is based on risk, informing how much rigor to apply. The tools and techniques from systems engineering offer a framework to organize projects with everyone speaking the same language to provide consistent and repeatable project success that satisfies the stakeholders’ needs and meets the mission. The classes have provided a framework with tools for communicating system design, requirements, verification and validation, and an operational context.

42 ENGINEERING↗
DOE OSTI2024

Design Load Basis Guidance for Distributed Wind Turbines

Aeroelastic modeling (AM) is the primary methodology for structural and performance assessment of any wind turbine. Nonetheless, the use of AM in the distributed wind (DW) industry sector is limited due to several challenges (Damiani, Davis, & Summerville, 2022). One of these challenges lies in the perceived complexity of generating a proper set of numerical simulations to extract and process the key outputs for component design and verification, and, ultimately, achieve certification. This makes it difficult to reliably predict the structural and performance response of small wind turbines. From the investigation carried out in (Damiani & Davis, 2022), it is apparent that many stakeholders in this sector believe that a comprehensive guide for developing a design load basis (DLB) for distributed wind turbines (DWTs) is necessary.

17 WIND ENERGY↗
DOE OSTI2024

Hardware Fuzzing with An Emulator

Bugs in digital logic have led to some significant security vulnerabilities. Hardware bugs are particularly troublesome since they cannot be easily patched. Additionally, if the bug is in the root of trust, all trust built upon it can be vulnerable. Traditional testing either require a deep knowledge of the system, creative attack vectors and lots of human interaction. This is not scalable as there are very few engineers that can wear the hat of a designer, a verification engineer, and a cybersecurity expert. Hardware fuzzing is a relatively new research area in dynamic hardware testing. It has proven to be an effective method for discovering bugs, unexpected behaviors, and security vulnerabilities in software. While hardware fuzzing is new to the hardware domain, it has a strong track record in software testing. Fuzzing is a testing technique that randomly mutates the input data to uncover bugs or vulnerabilities in the design. It is especially good at finding corner cases that test engineers can not envision. Another advantage over other dynamic testing techniques is that, if done well, deep knowledge of the design is not required. Additionally, fuzzing scales well. If the system is set up correctly, it can run unsupervised for weeks if necessary. In this work, we propose using hardware fuzzing to improve the input vector generation for an information flow tracking tool. To get reasonable throughput of test vectors, an emulator is targeted as the execution platform. Efficient emulator execution has some specific requirements.

42 ENGINEERING↗