Search NASA⌕ Search

SEARCH · Search NASA

Results for “FET”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
NASA NTRS2013

Folding Elastic Thermal Surface - FETS

The FETS is a light and compact thermal surface (sun shade, IR thermal shield, cover, and/or deployable radiator) that is mounted on a set of offset tape-spring hinges. The thermal surface is constrained during launch and activated in space by a thermomechanical latch such as a wax actuator. An application-specific embodiment of this technology developed for the MATMOS (Mars Atmospheric Trace Molecule Occultation Spectrometer) project serves as a deployable cover and thermal shield for its passive cooler. The FETS fits compactly against the instrument within the constrained launch envelope, and then unfolds into a larger area once in space. In this application, the FETS protects the passive cooler from thermal damage and contamination during ground operations, launch, and during orbit insertion. Once unfolded or deployed, the FETS serves as a heat shield, intercepting parasitic heat loads by blocking the passive cooler s view of the warm spacecraft. The technology significantly enhances the capabilities of instruments requiring either active or passive cooling of optical detectors. This can be particularly important for instruments where performance is limited by the available radiator area. Examples would be IR optical instruments on CubeSATs or those launched as hosted payloads because radiator area is limited and views are often undesirable. As a deployable radiator, the panels making up the FETS are linked thermally by thermal straps and heat pipes; the structural support and deployment energy is provided using tape-spring hinges. The FETS is a novel combination of existing technologies. Prior art for deployable heat shields uses rotating hinges that typically must be lubricated to avoid cold welding or static friction. By using tape-spring hinges, the FETS avoids the need for lubricants by avoiding friction altogether. This also eliminates the potential for contamination of nearby cooled optics by outgassing lubricants. Furthermore, the tape-spring design of the FETS is also self-locking so the panels stay in a rigid and extended configuration after deployment. This unexpected benefit makes the tape-spring hinge design of the FETS a light, simple, reliable, compact, non-outgassing hinge, spring, and latch. While tape-spring hinges are not novel, they have never been used to deploy passive unfolding thermal surfaces (radiator panels, covers, sun shades, or IR thermal shields). Furthermore, because this technology is compact, it has minimal impact on the launch envelope and mass specifications. FETS enhances the performance of hosted payload instruments where the science data is limited by dark noise. Incorporating FETS into a thermal control system increases radiator area, which lowers the optical detector temperature. This results in higher SNR (signal-to-noise ratio) and improved science data.

Urquiza, Eugenio↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2006

FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers

A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

Theofylaktos, Noulie↗
NASA NTRS1982

Ka-band Ga-As FET noise receiver/device development

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm.

Schellenberg, J. M.↗
NASA NTRS1997

Design, Fabrication and Evaluation of Deep Submicron FETs

GaAs FET's with gatelengths on a nanometer scale have been designed, fabricated and evaluated in order to investigate the limits of conventional GaAs scaling rules. An optimum layer structure for deep submicron GaAs MESFET's was designed, and a fabrication process that minimizes the effects of extrinsic parasitics was developed. The fabricated FET's were measured and evaluated at DC and at RF frequencies. 0.1 micron and 50 nm gatelength GaAs MESFET's with 2x45 micron wide "T"-shaped gates were fabricated so that a wide range of saturation current was achieved. For the 0.1 micron gatelength FET's, peak g(sub m,ext) varies from 611 mS/mm to 795 mS/mm with an average value of 717 mS/mm, peak f(sub t) varies from 90 GHz to 103 GHz with an average value of 96 GHz, and peak f(sub max) varies from 147 GHz to 172 GHz with an average value of 161 GHz. In comparison, the peak g(sub m,ext) of the 50 nm gatelength FET's is reduced by almost 20%, the peak f(sub t) is increased by 30%, and the peak f(sub max) is about the same as for the 0.1 micron gatelength FET's. The f(sub t) of the 50 nm gatelength FET's is higher than the f(sub t) of the 0.1 micron gatelength FET's because of the reduced gate-source capacitance (C(sub gs)). The peak f(sub max) does not show a similar improvement because of the onset of short channel effects.

Abbott-Morse, Tracy↗
NASA NTRS1983

EHF low-noise FET receiver

Extremely high frequency (EHF) receivers for military and NASA programs must be small, lightweight, and highly reliable. In connection with recent advances in the development of mm-wave FET devices and circuits, a basis has been obtained for the eventual replacement of diode mixer front-ends by FET preamplifiers in receivers up to 94 GHz. By placing a low noise amplifier in front of the mixer it is possible to achieve a lower system noise figure than that found in conventional mm-wave receivers. A broader bandwidth can also be provided. Attention is given to the receiver configuration, a low noise FET amplifier, an image rejection filter, a dual-gate FET mixer, a FET local oscillator, and a FET receiver.

Schellenberg, J. M.↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
DOE OSTI2023

Power converter with co-packaged secondary field effect transistors (FETs)

A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1983

The 20 GHz spacecraft FET solid state transmitter

The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band using GaAs field effect transistors (FETs) was detailed. The major efforts include GaAs FET device development, single-ended amplifier stage, balanced amplifier stage, cascaded stage and radial combiner designs, and amplifier integration and test. A multistage GaAs FET amplifier capable of 8.2 W CW output over the 17.9 to 19.1 GHz frequency band was developed. The GaAs FET devices developed represent state of the art FET power device technology. Further device improvements are necessary to increase the bandwidth to 2.5 GHz, improve dc-to-RF efficiency, and increase power capability at the device level. Higher power devices will simplify the amplifier combining scheme, reducing the size and weight of the overall amplifier.

Source record↗
DOE OSTI2020

Dielectrophoresis assisted rapid, selective and single cell detection of antibiotic resistant bacteria with G-FETs

Time-consuming, expensive and low sensitivity diagnostic methods used for monitoring bacterial infections lead to unnecessary or delays in prescription of the right antibiotic treatment. Determining an optimal clinical treatment requires rapid detection and identification of pathogenic bacteria and their sensitivity to specific antimicrobials. However, diagnostic devices that meet all of these criteria have proven elusive thus far. Graphene field effect transistors (G-FET) are a promising solution, since they are highly sensitive to chemical/biological modification, can have fast detection times and can be placed on different substrates. Here, by integrating specific peptide probes over G-FETs, we present a proof-of-concept study for species and strain specific label-free detection of clinical strains of pathogenic bacteria with high specificity and sensitivity. We found that pyrene-conjugated peptides immobilized on G-FETs were capable of detecting pathogenic Staphylococcus aureus at the single-cell level and discriminate against other gram-positive and gram-negative bacterial pathogens. A similar device was able to discriminate between antibiotic resistant and sensitive strains of Acinetobacter baumannii , suggesting that these devices can also be used for detecting antibiotic resistive pathogens. Furthermore, a new means of enhancing attachment, electric-field assisted binding, reduced the detection limit to 104 cells/ml and the detection time to below 5 minutes. Here, the combination of single step attachment, inexpensive production, rapid, selective and sensitive detection suggest G-FETs plus pyrene-conjugated peptides are a new platform for solving major challenges faced in point of care diagnostics to fight infectious diseases and antimicrobial resistance.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS1975

Theoretical transducer properties of piezoelectric insulator FET transducers

An oriented piezoelectric film incorporated in the insulator region of a silicon insulated-gate field-effect transistor (FET) results in a sensitive high-frequency strain transducer. Theory governing the transducer properties of the piezoelectric insulator FET transducer is presented. Equations are developed which relate the drain current of the device to induced polarizations of the piezoelectric layer. The highest frequency of surface strains to which the FET transducer can respond is determined by the FET frequency response - ultimately by the channel transit time. This frequency can extend to the GHz range. The low-frequency response to applied strain is determined by the dielectric relaxation frequency of the piezoelectric layer.

Greeneich, E. W.↗
NASA NTRS1984

GaAs dual-gate FET for operation up to K-band

A high-frequency equivalent-circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented. It is found that the gain of a dual-gate FET is higher than of a single-gate FET at low frequency but decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable-gain-amplifier applications up to K-band has been developed. At 10 GHz, a 1.2-mm-gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic-gain control range of up to 45 dB was obtained with an insertion phase change of no more than + or 2 degrees for the first 10 dB of gain control.

Kim, B.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
DOE OSTI2020

Nano-FET-enabled biosensors: Materials perspective and recent advances in North America

Field-effect transistor (FET) is a very promising platform for biosensor applications due to its magnificent properties, including label-free detection, high sensitivity, fast response, real-time measurement capability, low running power, and the feasibility to miniaturize to a portable device. 1D (e.g. carbon nanotubes, Si nanowires, conductive polymer nanowires, 1D metal oxides, and others) and 2D (e.g. graphene materials, transition metal dichalcogenides, black phosphorus, and 2D metal oxides) materials, with their unique structural and electronic properties that are unavailable in bulk materials, have helped improve the sensitivity of FET biosensors and enabled detection down to single molecule. In this article, we give insights into the rapidly evolving field of 1D and 2D materials-based FET biosensors, with an emphasis on structure and electronic properties, synthesis, and biofunctionalization approaches of these nanomaterials. In addition, the progress in the 1D/2D-FET biosensors in North America, in the last decade, is summarized in tables. Moreover, challenges and future perspectives of 1D/2D-FET biosensors are covered.

1D materials↗
DOE OSTI2025

Extreme Enhancement-Mode Operation Accumulation Channel Hydrogen-Terminated Diamond FETs with V th < -6 V and High on-Current

In this work, a new Field Effect Transistor device concept based on hydrogen-terminated diamond (H-diamond) is demonstrated that operates in an Accumulation Channel rather than a Transfer Doping regime. The FET devices demonstrate both extreme enhancement-mode operation and high on-current with improved channel charge mobility compared to Transfer-Doped equivalents. Electron-beam evaporated Al 2 O 3 is used on H-diamond to suppress the Transfer Doping mechanism and produce an extremely high ungated channel resistance. A high-quality H-diamond surface with an unpinned Fermi level is crucially achieved, allowing for the formation of a high-density hole accumulation layer by gating the entire device channel which is encapsulated in dual-stacks of Al 2 O 3 . Completed devices with gate/channel length of 1 µm demonstrate record threshold voltage < -6 V with on-current > 80 mA mm -1 . Carrier density and mobility figures extracted by CV analysis indicate a high 2D charge density of ≈ 2 × 10 12 cm -2 and increased hole mobility of 110 cm 2 V -1 s -1 in comparison with more traditional Transfer-Doped H-diamond FETs. These results demonstrate the most negative threshold voltage yet reported for H-diamond FETs and highlight a powerful new strategy to greatly improve carrier mobility and enable enhanced high power and high frequency diamond transistor performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗
NASA NTRS1983

Design considerations for FET-gated power transistors

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Chen, D. Y.↗