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At least 19 records

Characterization of the faulted behavior of digital computers and fault tolerant systems

A development status evaluation is presented for efforts conducted at NASA-Langley since 1977, toward the characterization of the latent fault in digital fault-tolerant systems. Attention is given to the practical, high speed, generalized gate-level logic system simulator developed, as well as to the validation methodology used for the simulator, on the basis of faultable software and hardware simulations employing a prototype MIL-STD-1750A processor. After validation, latency tests will be performed.

Bavuso, Salvatore J.↗

Transient fault behavior in a microprocessor: A case study

An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made.

Duba, Patrick↗

A renormalization group model for the stick-slip behavior of faults

A fault which is treated as an array of asperities with a prescribed statistical distribution of strengths is described. For a linear array the stress is transferred to a single adjacent asperity and for a two dimensional array to three ajacent asperities. It is shown that the solutions bifurcate at a critical applied stress. At stresses less than the critical stress virtually no asperities fail on a large scale and the fault is locked. At the critical stress the solution bifurcates and asperity failure cascades away from the nucleus of failure. It is found that the stick slip behavior of most faults can be attributed to the distribution of asperities on the fault. The observation of stick slip behavior on faults rather than stable sliding, why the observed level of seismicity on a locked fault is very small, and why the stress on a fault is less than that predicted by a standard value of the coefficient of friction are outlined.

Smalley, R. F., Jr.↗

A renormalization group approach to the stick-slip behavior of faults

A fault which is treated as an array of asperities with a perscribed statistical distribution of strengths is described. For a linear array the stress is transferred to a single adjacent asperity and for a two dimensional array to three adjacent asperities. It is shown that the solutions bifurcate at a critical applied stress. At stresses less than the critical stress virtually no asperities fail on a large scale and the fault is locked. At the critical stress the solution bifurcates and asperity failure cascades away from the nucleus of failure. It is found that the stick slip behavior of most faults can be attributed to the distribution of asperities on the fault. The observation of stick slip behavior on faults rather than stable sliding, why the observed level of seismicity on a locked fault is very small, and why the stress on a fault is less than that predicted by a standard value of the coefficient of friction are outlined.

Smalley, R. F., Jr.↗

Fault-free behavior of reliable multiprocessor systems: FTMP experiments in AIRLAB

This report describes a set of experiments which were implemented on the Fault tolerant Multi-Processor (FTMP) at NASA/Langley's AIRLAB facility. These experiments are part of an effort to formulate and evaluate validation methodologies for fault-tolerant computers. This report deals with the measurement of single parameters (baselines) of a fault free system. The initial set of baseline experiments lead to the following conclusions: (1) The system clock is constant and independent of workload in the tested cases; (2) the instruction execution times are constant; (3) the R4 frame size is 40mS with some variation; (4) the frame stretching mechanism has some flaws in its implementation that allow the possibility of an infinite stretching of frame duration. Future experiments are planned. Some will broaden the results of these initial experiments. Others will measure the system more dynamically. The implementation of a synthetic workload generation mechanism for FTMP is planned to enhance the experimental environment of the system.

Clune, E.↗

Validation of fault-free behavior of a reliable multiprocessor system - FTMP: A case study

A program of experiments has been conducted at NASA-Langley to test the fault-free performance of a Fault-Tolerant Multiprocessor (FTMP) avionics system for next-generation aircraft. Baseline measurements of an operating FTMP system were obtained with respect to the following parameters: instruction execution time, frame size, and the variation of clock ticks. The mechanisms of frame stretching were also investigated. The experimental results are summarized in a table. Areas of interest for future tests are identified, with emphasis given to the implementation of a synthetic workload generation mechanism on FTMP.

Clune, E.↗

Ab-Initio Study of Stacking Fault Segregation Behavior in Ni-based Superalloys at High Temperatures

Ni-based superalloys demonstrate extraordinary creep properties compared to traditional metallic systems due to the formation of L12 (γ’) precipitates. Despite experimental evidence of alloying element segregation to the stacking faults, prior ab-initio efforts indicated repulsion of Nb from superlattice intrinsic stacking faults (SISFs) . Due to the importance of this element in key strengthening mechanisms, we developed a new technique to account for multi-component segregation behavior at temperature combining ab-initio molecular dynamics (AIMD) and Monte-Carlo (MC) simulations. Using this technique, we replicated experimentally observed segregation behavior of Nb, Co, and Ti to the SISF in L12 (Figure 1). Furthermore, we investigated the co-segregation behaviors of individual pairs of alloying elements to determine the interaction effects which lead to this segregation behavior in the full alloy system. By simulating the reduced-chemistry models using our approach, we reconciled previous ab-initio calculations demonstrating repulsion of Nb from the SISF and the experimentally observed segregation behavior.

Molecular Dynamics↗

Parameter Transient Behavior Analysis on Fault Tolerant Control System

In a fault tolerant control (FTC) system, a parameter varying FTC law is reconfigured based on fault parameters estimated by fault detection and isolation (FDI) modules. FDI modules require some time to detect fault occurrences in aero-vehicle dynamics. This paper illustrates analysis of a FTC system based on estimated fault parameter transient behavior which may include false fault detections during a short time interval. Using Lyapunov function analysis, the upper bound of an induced-L2 norm of the FTC system performance is calculated as a function of a fault detection time and the exponential decay rate of the Lyapunov function.

Belcastro, Christine↗

Error latency estimation using functional fault modeling

A complete modeling of faults at gate level for a fault tolerant computer is both infeasible and uneconomical. Functional fault modeling is an approach where units are characterized at an intermediate level and then combined to determine fault behavior. The applicability of functional fault modeling to the FTMP is studied. Using this model a forecast of error latency is made for some functional blocks. This approach is useful in representing larger sections of the hardware and aids in uncovering system level deficiencies.

Manthani, S. R.↗

Learning and diagnosing faults using neural networks

Neural networks have been employed for learning fault behavior from rocket engine simulator parameters and for diagnosing faults on the basis of the learned behavior. Two problems in applying neural networks to learning and diagnosing faults are (1) the complexity of the sensor data to fault mapping to be modeled by the neural network, which implies difficult and lengthy training procedures; and (2) the lack of sufficient training data to adequately represent the very large number of different types of faults which might occur. Methods are derived and tested in an architecture which addresses these two problems. First, the sensor data to fault mapping is decomposed into three simpler mappings which perform sensor data compression, hypothesis generation, and sensor fusion. Efficient training is performed for each mapping separately. Secondly, the neural network which performs sensor fusion is structured to detect new unknown faults for which training examples were not presented during training. These methods were tested on a task of fault diagnosis by employing rocket engine simulator data. Results indicate that the decomposed neural network architecture can be trained efficiently, can identify faults for which it has been trained, and can detect the occurrence of faults for which it has not been trained.

Whitehead, Bruce A.↗

Faulty behavior of asynchronous storage elements

It is often assumed that the faults in storage elements (SE's) can be modeled as output/input stuck-at-faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. A more accurate higher level fault model for elementary SE's used in asynchronous circuits is presented. This model offers better representation of the physical failures. It is shown that the stuck-at model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SE's that are not covered by the stuck-at model. These include data-feed-through behaviors that cause the SE to be combinational. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit.

Al-Assadi, Waleed K.↗

Earthquake deformation cycle in the Andean Back Arc, western Argentina

It is pointed out that the 1977 Caucete earthquake was an east-west compressive event which occurred at a depth of about 17 km in the Andean back arc approximately 450 km east of the Chile trench. The present study is primarily concerned with the mechanics of fault behavior prior to and after the 1977 earthquake, as evidenced by preseismic and postseismic vertical deformation. Simple fault models for each phase of deformation are presented. The models of preseismic slip, coseismic slip, and postseismic slip consist of uniform dislocations in an elastic half-space following the method of Chinnery (1961). The basically elastic models presented demonstrate that deformations in the vicinity of the 1977 Caucete, Argentina, earthquake are consistent with activity on some portion of the coseismic fault. This is evidence that these deformations are directly related to the processes of strain accumulation and release associated with the event.

Reilinger, R.↗

Architectural Modeling and Analysis for Safety Engineering

Model-based development tools are increasingly being used for system-level development of safety-critical systems. Architectural and behavioral models provide important information that can be leveraged to improve the system safety analysis process. Model-based design artifacts produced in early stage development activities can be used to perform system safety analysis, reducing costs and providing accurate results throughout the system life-cycle. In this report we describe an extension to the Architecture Analysis and Design Language (AADL) that supports modeling of system behavior under failure conditions. This Safety Annex enables the independent modeling of component failures and allows safety engineers to weave various types of fault behavior into the nominal system model. The accompanying tool support uses model checking to propagate errors from their source to their effect on safety properties without the need to add separate propagation specifications. The tool also captures all minimal set of fault combinations that can cause violation of the safety properties, that can be compared to qualitative and quantitative objectives as part of the safety assessment process. We describe the Safety Annex, illustrate its use with a representative example, and discuss and demonstrate the tool support enabling an analyst to investigate the system behavior under failure conditions.

FTA↗

Model-Based Verification and Validation of Spacecraft Avionics

Verification and Validation (V&V) at JPL is traditionally performed on flight or flight-like hardware running flight software. For some time, the complexity of avionics has increased exponentially while the time allocated for system integration and associated V&V testing has remained fixed. There is an increasing need to perform comprehensive system level V&V using modeling and simulation, and to use scarce hardware testing time to validate models; the norm for thermal and structural V&V for some time. Our approach extends model-based V&V to electronics and software through functional and structural models implemented in SysML. We develop component models of electronics and software that are validated by comparison with test results from actual equipment. The models are then simulated enabling a more complete set of test cases than possible on flight hardware. SysML simulations provide access and control of internal nodes that may not be available in physical systems. This is particularly helpful in testing fault protection behaviors when injecting faults is either not possible or potentially damaging to the hardware. We can also model both hardware and software behaviors in SysML, which allows us to simulate hardware and software interactions. With an integrated model and simulation capability we can evaluate the hardware and software interactions and identify problems sooner. The primary missing piece is validating SysML model correctness against hardware; this experiment demonstrated such an approach is possible.

MBV&V↗

The SURE approach to reliability analysis

The SURE computer program, a reliability-analysis tool for ultrareliable computer-system architectures, provides rapid computational capability for semi-Markov models useful in describing the fault-handling behavior of fault-tolerant computer systems. The basic mathematics of SURE and its user interface are described, including a sample interactive session. The basis of the SURE model-pruning capability is presented, and the SURE loop-truncation method is justified. The techniques used to develop a semi-Markov model of a fault-tolerant computer system are also reviewed.

Butler, Ricky W.↗

Case-based approach to handling aircraft malfunctions

Reasoning about physical systems in operation is a difficult task, and any attempt to automate the process must overcome the problems of modeling normal behavior, diagnosing faults, and predicting future behavior. This paper describes a prototypical case-based reasoner (CBR) that operates in the domain of in-flight fault diagnosis and prognosis of aviation subsystems, particularly jet engines. The reasoner operates on the observation that the ability of a CBR program to reason about physical systems can be significantly enhanced by the addition to the CBR program of a model of the physical system to describe the system's structural, functional, and causal behavior.

Karamouzis, Stamos T.↗