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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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16 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level

Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.

Dual-metal gate work functions↗
DOE OSTI2023

Simulation of gallium nitride vertical fin-shaped field effect transistor for use as thermal neutron detector

Through the use of a radiation detection system simulation framework, a gallium nitride vertical fin-shaped field effect transistor (FinFET) was studied for output response when utilized as a thermal neutron detector. The FinFET was assumed to had been backfilled with boron carbide, reactive to thermal neutrons. The GaN FinFET was modeled with radiation transport from MCNP, and the electronic transport from COMSOL Multiphysics. Fabricated FinFET devices (not neutron reactive) were tested to aid in the tuning of the COMSOL FinFET model. Through time-depenent studies, the drain current response pulse to simulated ionization due to single events lead to building of a database of device responses to radiation. By integrating the current pulses over time, the induced charge was calculated. Using the results of the radiation transport PTRAC file in combination with the induced charge database, an integrated charge spectrum was calculated.

Davidson, Bryce L.↗
DOE OSTI2024

The Effects of Threshold Voltage and Number of Fins per Transistor on the TID Response of GF 12LP Technology

This abstract presents a comprehensive analysis of total ionizing dose (TID) response in GlobalFoundries’ 12LP 12nm bulk FinFET technology using 10keV X-rays. Devices with higher threshold voltages (VTs) demonstrated lower increases in off-state leakage current (IDS,OFF) post-irradiation, highlighting the mitigating role of high VT in TID response. Our data shows that transistors with fewer fins exhibit superior TID resistance, implying lower susceptibility to radiation effects. Our study also probed two bias conditions, "Gate-On" and "Pass-Gate," with the former displaying more severe TID degradation. Interestingly, p-type devices displayed negligible degradation, underscoring their inherent resilience to TID effects. Additionally, medium thick n-type devices echoed the fin-count-dependent TID response observed in other transistor types, further strengthening our findings. These results underscore the importance of strategic transistor selection and design for enhancing the TID resilience of future CMOS FinFET architectures, particularly critical in radiation-intense environments.

42 ENGINEERING↗
DOE OSTI2026

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗
NASA NTRS2016

Radiation Failures in Intel 14nm Microprocessors

In this study the 14 nm Intel Broadwell 5th generation core series 5005U-i3 and 5200U-i5 was mounted on Dell Inspiron laptops, MSI Cubi and Gigabyte Brix barebones and tested with Windows 8 and CentOS7 at idle. Heavy-ion-induced hard- and catastrophic failures do not appear to be related to the Intel 14nm Tri-Gate FinFET process. They originate from a small (9 m 140 m) area on the 32nm planar PCH die (not the CPU) as initially speculated. The hard failures seem to be due to a SEE but the exact physical mechanism has yet to be identified. Some possibilities include latch-ups, charge ion trapping or implantation, ion channels, or a combination of those (in biased conditions). The mechanism of the catastrophic failures seems related to the presence of electric power (1.05V core voltage). The 1064 nm laser mimics ionization radiation and induces soft- and hard failures as a direct result of electron-hole pair production, not heat. The 14nm FinFET processes continue to look promising for space radiation environments.

Microprocessors↗
DOE OSTI2023

Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach

Parameter extraction of compact transistor models is an expensive process, heavily relying on engineering knowledge and experience. To automate such a process, we propose a novel approach, Graph-based Compact Model (GCM), that integrates physical modeling and data-driven learning. GCM utilizes Graph Neural Networks (GNNs) to establish the model structure, while retaining the physicality in compact models. Here, we implement our GCM in Verilog-A to support circuit simulations. As demonstrated with an academic 7 nm FinFET PDK, the new approach automatically generates a GCM model within a minute, and achieves excellent accuracy and efficiency in SPICE.

42 ENGINEERING↗
DOE OSTI2024

Self-aligned fabrication of vertical, fin-based structures

Modern power devices rely on complex, three-dimensional, vertical designs to increase their power density, ease their thermal management, and improve their reliability. However, fabrication techniques have historically relied on 2D processes for patterning lateral features. This work presents a new technology that uses multiple steps of angled depositions to fabricate self-aligned vertical, fin-based devices that avoid fundamental lithography resolution and alignment limitations. The fabrication flows of two devices, the self-aligned vertical finFET and the high-κ dielectric fin diode, are presented to demonstrate how angled depositions can readily achieve transistors with submicrometer, vertical gates in a source-first process and also create high-aspect ratio GaN fins with a record 70:1 aspect ratio.

Perozek, Joshua (ORCID:0000000251519131)↗