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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗
DOE OSTI2019

Extreme Temperature Operation of Ultra-Wide Bandgap AlGaN High Electron Mobility Transistors

High Aluminum content channel (Al 0.85 Ga 0.15 N/Al -0.7 Ga 0.3 N) High Electron Mobility Transistors (HEMTs) were operated from room temperature to 500°C in ambient. The devices exhibited only moderate reduction, 58%, in on-state forward current. Gate lag measurements at 100 kHz and 10% duty only showed a slight reduction in pulsed current from DC at 500°C and high gate voltages. Interfacial trap densities were 2 × 10 11 over the range 25-300°C and 3 × 10 12 cm -2 from 300-500°C from the subthreshold swing. These low interfacial trap densities and the near ideal gate lag measurement indicate high-quality epi layers. The insulating properties of the barrier layer led to low gate induced drain leakage current of ~10 -12 A/mm and ~10 -8 A/mm at 25 and 500°C, respectively. Low leakage current was enabled by the high Schottky barrier of the Ni/Au gate, 1.1 eV and 3.3 eV at 25 and 500°C, respectively. These properties of the AlGaN channel HEMTs demonstrate their potential for high power and high temperature operation.

36 MATERIALS SCIENCE↗
DOE OSTI2015

O{sub 3}-sourced atomic layer deposition of high quality Al{sub 2}O{sub 3} gate dielectric for normally-off GaN metal-insulator-semiconductor high-electron-mobility transistors

High quality Al{sub 2}O{sub 3} film grown by atomic layer deposition (ALD), with ozone (O{sub 3}) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al–O–H and Al–Al bonds in ALD-Al{sub 2}O{sub 3} has been realized by substituting conventional H{sub 2}O source with O{sub 3}. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O{sub 3}-Al{sub 2}O{sub 3} and 2-nm H{sub 2}O-Al{sub 2}O{sub 3} interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 × 10{sup 12 }cm{sup −2}, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance R{sub ON,sp} of 0.49 mΩ cm{sup 2}.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

An AlN/Al 0.85 Ga 0.15 N high electron mobility transistor

An AlN barrier high electron mobility transistor (HEMT) based on the AlN/Al 0.85 Ga 0.15 N heterostructure was grown, fabricated, and electrically characterized, thereby extending the range of Al composition and bandgap for AlGaN channel HEMTs. An etch and regrowth procedure was implemented for source and drain contact formation. A breakdown voltage of 810 V was achieved without a gate insulator or field plate. Excellent gate leakage characteristics enabled a high I on /I off current ratio greater than 10 7 and an excellent subthreshold slope of 75 mV/decade. A large Schottky barrier height of 1.74 eV contributed to these results. In conclusion, the room temperature voltage-dependent 3-terminal off-state drain current was adequately modeled with Frenkel-Poole emission.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Investigation of abrupt degradation of drain current caused by under-gate crack in AlGaN/GaN high electron mobility transistors during high temperature operation stress

In this paper, we investigate the degradation mode and mechanism of AlGaN/GaN based high electron mobility transistors (HEMTs) during high temperature operation (HTO) stress. It demonstrates that there was abrupt degradation mode of drain current during HTO stress. The abrupt degradation is ascribed to the formation of crack under the gate which was the result of the brittle fracture of epilayer based on failure analysis. The origin of the mechanical damage under the gate is further investigated and discussed based on top-down scanning electron microscope, cross section transmission electron microscope and energy dispersive x-ray spectroscopy analysis, and stress simulation. Based on the coupled analysis of the failure physical feature and stress simulation considering the coefficient of thermal expansion (CTE) mismatch in different materials in gate metals/semiconductor system, the mechanical damage under the gate is related to mechanical stress induced by CTE mismatch in Au/Ti/Mo/GaN system and stress concentration caused by the localized structural damage at the drain side of the gate edge. These results indicate that mechanical stress induced by CTE mismatch of materials inside the device plays great important role on the reliability of AlGaN/GaN HEMTs during HTO stress.

36 MATERIALS SCIENCE↗
DOE OSTI2012

Effect of buffer structures on AlGaN/GaN high electron mobility transistor reliability

AlGaN/GaN high electron mobility transistors (HEMTs) with three different types of buffer layers, including a GaN/AlGaN composite layer, or 1 or 2 lm GaN thick layers, were fabricated and their reliability compared. The HEMTs with the thick GaN buffer layer showed the lowest critical voltage (Vcri) during off-state drain step-stress, but this was increased by around 50% and 100% for devices with the composite AlGaN/GaN buffer layers or thinner GaN buffers, respectively. The Voff - state for HEMTs with thin GaN and composite buffers were 100 V, however, this degraded to 50 60V for devices with thick GaN buffers due to the difference in peak electric field near the gate edge. A similar trend was observed in the isolation breakdown voltage measurements, with the highest Viso achieved based on thin GaN or composite buffer designs (600 700 V), while a much smaller Viso of 200V was measured on HEMTs with the thick GaN buffer layers. These results demonstrate the strong influence of buffer structure and defect density on AlGaN/GaN HEMT performance and reliability.

Liu, L.↗
DOE OSTI2019

Heavy ion irradiation effects on GaN/AlGaN high electron mobility transistor failure at off-state

We investigate the effects of ion irradiation on AlGaN/GaN high electron mobility electron transistors using in-situ transmission electron microscopy. The experiments are performed inside the microscope to visualize the defects, microstructure and interfaces of ion irradiated transistors during operation and failure. Here, experimental results indicate that heavy ions such as Au 4+ can create a significant number of defects such as vacancies, interstitials and dislocations in the device layer. It is hypothesized that these defects act as charge traps in the device layer and the resulting charge accumulation lowers the breakdown voltage. Sequential energy dispersive X-ray spectroscopy mapping allows us to track individual chemical elements during the experiment, and the results suggest that the electrical degradation in the device layer may originate from oxygen and nitrogen vacancies.

36 MATERIALS SCIENCE↗
DOE OSTI2017

High Temperature Operation of Al 0.45 Ga 0.55 N/Al 0.30 Ga 0.70 N High Electron Mobility Transistors

AlGaN-channel high electron mobility transistors (HEMTs) are among a class of ultra wide-bandgap transistors that have a bandgap greater than ~3.4 eV, beyond that of GaN and SiC, and are promising candidates for RF and power applications. Long-channel Al x Ga 1-x N HEMTs with x = 0.3 in the channel have been built and evaluated across the -50°C to +200°C temperature range. Room temperature drain current of 70 mA/mm, absent of gate leakage, and with a modest -1.3 V threshold voltage was measured. A very large I on /I off current ratio, greater than 10 8 was demonstrated over the entire temperature range, indicating that off-state leakage is below the measurement limit even at 200°C. Finally, combined with near ideal subthreshold slope factor that is just 1.3× higher than the theoretical limit across the temperature range, the excellent leakage properties are an attractive characteristic for high temperature operation.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Ultra-low noise high electron mobility transistors for high-impedance and low-frequency deep cryogenic readout electronics

We report on the results obtained from specially designed high electron mobility transistors at 4.2 K: the gate leakage current can be limited lower than 1 aA, and the equivalent input noise-voltage and noise-current at 1 Hz can reach 6.3 nV/Hz{sup 1∕2} and 20 aA/Hz{sup 1∕2}, respectively. These results open the way to realize high performance low-frequency readout electronics under very low-temperature conditions.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Electrical and structural degradation of GaN high electron mobility transistors under high-power and high-temperature Direct Current stress

We have stressed AlGaN/GaN HEMTs (High Electron Mobility Transistors) under high-power and high-temperature DC conditions that resulted in various levels of device degradation. Following electrical stress, we conducted a well-established three-step wet etching process to remove passivation, gate and ohmic contacts so that the device surface can be examined by SEM and AFM. We have found prominent pits and trenches that have formed under the gate edge on the drain side of the device. The width and depth of the pits under the gate edge correlate with the degree of drain current degradation. In addition, we also found visible erosion under the full extent of the gate. The depth of the eroded region averaged along the gate width under the gate correlated with channel resistance degradation. Both electrical and structural analysis results indicate that device degradation under high-power DC conditions is of a similar nature as in better understood high-voltage OFF-state conditions. The recognition of a unified degradation mechanism provides impetus to the development of a degradation model with lifetime predictive capabilities for a broad range of operating conditions spanning from OFF-state to ON-state.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Time evolution of off-state degradation of AlGaN/GaN high electron mobility transistors

The evolution of AlGaN/GaN high electron mobility transistors under off-state stress conditions is studied by gate leakage current (I{sub g}) monitoring, electroluminescence (EL), and atomic force microscope (AFM) imaging at room temperature. It is found that the number of off-state failure sites as identified by EL increases over time during stress until it reaches a saturation value. I{sub g} increases accordingly during stress until this saturation number of failure sites is reached. AFM scanning of the device surface stripped of metal contacts and passivation reveals surface pits corresponding to the location of the EL spots. These pits have an elongated shape oriented towards the drain contact whose length is correlated with the distance to the adjacent pits and with the time since their appearance during the stress experiment. A model for the generation and evolution of the off-state stress-related failure sites is proposed consistent with the experimental results, bringing together surface migration of electrochemical species with trap-based leakage mechanisms and resulting in the formation of an exclusion zone around each failure site.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2012

Transmission electron microscopy characterization of electrically stressed AlGaN/GaN high electron mobility transistor devices

A set of AlGaN/GaN high electron mobility transistor devices has been investigated using step-stress testing, and representative samples of undegraded, source-side-degraded, and drain-side-degraded devices were examined using electron microscopy and microanalysis. An unstressed reference sample was also examined. All tested devices and their corresponding transmission electron microscopy samples originated from the same wafer and thus received nominally identical processing. Step-stressing was performed on each device and the corresponding current voltage characteristics were generated. Degradation in electrical performance, specifically greatly increased gate leakage current, was shown to be correlated with the presence of crystal defects near the gate edges. However, the drain-side-degraded device showed a surface pit on the source side, and another region of the same device showed no evidence of damage. Moreover, significant metal diffusion into the barrier layer from the gate contacts was also observed, as well as thin amorphous oxide layers below the gate metal contacts, even in the unstressed sample. Overall, these observations emphasize that gate-edge defects provide only a partial explanation for device failure.

Johnson, Michael↗
DOE OSTI2014

Impact of barrier thickness on transistor performance in AlN/GaN high electron mobility transistors grown on free-standing GaN substrates

A series of six ultrathin AlN/GaN heterostructures with varied AlN thicknesses from 1.5–6 nm have been grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. High electron mobility transistors (HEMTs) were fabricated from the set in order to assess the impact of barrier thickness and homo-epitaxial growth on transistor performance. Room temperature Hall characteristics revealed mobility of 1700 cm{sup 2}/V s and sheet resistance of 130 Ω/□ for a 3 nm thick barrier, ranking amongst the lowest room-temperature sheet resistance values reported for a polarization-doped single heterostructure in the III-Nitride family. DC and small signal HEMT electrical characteristics from submicron gate length HEMTs further elucidated the effect of the AlN barrier thickness on device performance.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2016

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗