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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Implement-Only Implementation of a Multi Pressure Rail System to an Agricultural Planter

Tightening emissions regulations and rising fuel costs have driven a desire across many industries for more efficient actuation systems. This is particularly true of the agricultural sector. An extremely common arrangement in this sector is the tractor and implement pairing, in which actuators on an implement are powered by a hydraulic supply system on the towing tractor. This arrangement complicates the development of energy efficient hydraulic systems, as many new system designs require modification of both machines to reap efficiency benefits. Past work by the authors’ team has demonstrated great potentials for Multi-Pressure-Rail (MPR) technology involving both the tractor and implement subsystems. However, applicability of this MPR technology in a more realistic scenario where only one vehicle is equipped with such technology was not addressed. This work proposes an implementation of the MPR technology to an agricultural planter that allows significant savings, while only modifying the implement machine. This is done by manipulating the load sense network of a stock tractor to set system pressures to those required by the MPR system. This greatly reduces the barrier to implementation of MPR technology in agriculture. The work begins by outlining the reference machine for the system, then reviews the MPR system working principle. After this, the proposed expansion to the MPR concept is laid out, and applied to the reference system. Finally, experimental validation is carried out, demonstrating on average 37% reduction in system power consumption.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2025

SITCOMTN-162: Testing the implementation of Metadetection and Cell-Based Coadds on Abell 360 LSSTComCam data

The purpose of this technote is to test the technical quality of LSSTComCam commissioning data, specifically the Rubin_SV_38_7 field, by utilizing cell-based coadds and Metadetection by measuring the tangential and cross weak lensing shear profiles of the massive cluster Abell 360 (called A360 throughout the technote). The process entails generating the cell-based coadds for Metadetection to run on, identifying and removing cluster member galaxies, applying quality cuts, calibrating the shear measurements, and validation. Cell-based coadds and Metadetection are both currently in the process of being implemented within the LSST Science Pipelines at the time of this technote. There is substantial technical value in attempting a difficult measurement prior to full implementation. Measuring the tangential shear around A360 will showcase the current abilities of these algorithms, as well as highlight where work is still needed. As seen from the resulting shear profile of A360, the cell-based coadds and Metadetection are able to work in tandem to produce a shear catalog and resulting reduced shear profile. This technote is one part of a series studying A360 in order to both stress test the commissioning camera and demonstrate the technical capabilities of the Vera Rubin Observatory. We study the quality of the PSF modeling and impact it can have on cluster WL in [Combet et al., 2025], implementation of cell-based coadds and subsequent use for Metadetect [Sheldon et al., 2023] in this technote, photometric calibration in (in prep), source selection and photometric redshifts in [Adari et al., 2025], use of Anacal [Li et al., 2024] to produce a cluster shear profile in [Li et al., 2025], and background subtraction in this field and Fornax in [Zhou et al., 2025].

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2026

Fermilab PIP-II machine protection system digitized data noise elimination scheme and its FPGA implementation

In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can contaminate the data. To suppress noise across these ranges—especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies—advanced digital processing beyond standard filtering is required. Several real-time functional blocks were simulated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid baseline by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance and were successfully implemented on a low-cost FPGA.

Wu, Jinyuan [Fermilab]↗
NASA NTRS1993

Explicit robust schemes for implementation of a class of principal value-based constitutive models: Symbolic and numeric implementation

The issue of developing effective and robust schemes to implement a class of the Ogden-type hyperelastic constitutive models is addressed. To this end, special purpose functions (running under MACSYMA) are developed for the symbolic derivation, evaluation, and automatic FORTRAN code generation of explicit expressions for the corresponding stress function and material tangent stiffness tensors. These explicit forms are valid over the entire deformation range, since the singularities resulting from repeated principal-stretch values have been theoretically removed. The required computational algorithms are outlined, and the resulting FORTRAN computer code is presented.

Arnold, S. M.↗
DOE OSTI2026

The Energy Costs of Dewatering Feedstock Microalgae Species Using Conventional Implementations of Ultrasonic and Crossflow Filtration Technologies

The use of microalgae as a feedstock for biofuels and other products continues to be explored, but large-scale biomass production faces persistent high costs. One major cost contributor is the energy required for harvesting and dewatering, a challenge resulting from the dilute nature of microalgae cultures as well as the properties of microalgae cells. This study investigated the energy demands of concentrating three diverse microalgae species (Nannochloropsis salina, Scenedesmus obliquus, and Chlorella luteoviridis) exhibiting different settling velocities, a key harvesting property, using conventional ultrasonic and crossflow membrane filtration. Membrane-free ultrasonic filtration removed 60-80% of the microalgae largely in steady-state operations, increasing concentrations 20-100 times, while consuming 1-6 kWh/m3 - similar to centrifugation. In contrast, crossflow membrane filtration retained nearly 100% of the microalgae, increasing concentrations over 20-fold, but consumed 158 kWh/m3 - over 10 times the energy of centrifugation. Both approaches exceeded the 10% energy target suggested in the 2010 National Algal Biofuel Technology Roadmap. This study also highlights potential sources of energy savings. For ultrasonic filtration, attention to an innovative, dynamic property of the ultrasonic chamber called the Energy Efficiency Factor, could lead to energy reductions by no more than 10-fold and improve the favorability of two of the microalgae species studied. For membrane filtration, a dead-end configuration could reduce energy consumption by no more than 1000-fold, making it favorable for all three species. This study not only highlights the need to further increase the energy content of microalgae cultures, but also the critical importance of continued development of ultrasonic filtration and other harvesting technologies to achieve low-cost, energy-sustainable algal biofuels.

09 BIOMASS FUELS↗
DOE OSTI2026

Implementation of a 1550-nm laser system for beam characterization at the Argonne Wakefield Accelerator

Accurately recording an electron bunch’s longitudinal profile is an important diagnostic for wakefield accelerators employing shaped bunches to increase transformer ratios. Electro-optic sampling of terahertz radiation from the bunch is an attractive approach due to its non-destructive nature. In preparation for future characterization experiments, the Argonne Wakefield Accelerator test facility has recently installed a 1550 nm laser system, including the necessary support systems to synchronize with the photoinjector laser system at 81.25 MHz. We report here on the initial installation and synchronization demonstrations.

Ody, Alexander [Argonne, PHY]↗
DOE OSTI2025

Comparing computational times for simulations when using PBPK model template and stand-alone implementations of PBPK models

Introduction We previously developed a PBPK model template that consists of a single model “superstructure” with equations and logic found in many physiologically based pharmacokinetic (PBPK) models. Using the template, one can implement PBPK models with different combinations of structures and features. Methods To identify factors that influence computational time required for PBPK model simulations, we conducted timing experiments using various implementations of PBPK models for dichloromethane and chloroform, including template and stand-alone implementations, and simulating four different exposure scenarios. For each experiment, we measured the required computational time and evaluated the impacts of including various model features (e.g., number of output variables calculated) and incorporating various design choices (e.g., different methods for estimating blood concentrations). Results We observed that model implementations that treat body weight and dependent quantities as constant (fixed) parameters can result in a 30% time savings compared with options that treat body weight and dependent quantities as time-varying. We also observed that decreasing the number of state variables by 36% in our PBPK model template led to a decrease of 20–35% in computational time. Other factors, such as the number of output variables, the method for implementing conditional statements, and the method for estimating blood concentrations, did not have large impacts on simulation time. In general, simulations with PBPK model template implementations of models required more time than simulations with stand-alone implementations, but the flexibility and (human) time savings in preparing and reviewing a model implemented using the PBPK model template may justify the increases in computational time requirements. Conclusion Our findings concerning how PBPK model design and implementation decisions impact computational speed can benefit anyone seeking to develop, improve, or apply a PBPK model, with or without the PBPK model template.

Bernstein, Amanda S.↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS2018

Know Your Enemy - Implementation of Bioremediation within a Suspected DNAPL Source Zone Following High-Resolution Site Characterization at Contractors Road Heavy Equipment Area, Kennedy Space Center, Florida

The National Aeronautics and Space Administration (NASA), Kennedy Space Center (KSC), has adopted high-resolution site characterization (HRSC) sampling techniques during baseline sampling prior to implementation of remedies to confirm and refine the conceptual site model (CSM). HRSC sampling was performed at Contractors Road Heavy Equipment Area (CRHE) prior to bioremediation implementation to verify the extent of the trichloroethene (TCE) dense non-aqueous phase liquid (DNAPL) source area (defined as the area with TCE concentrations above 1% solubility) and its daughter product dissolved plume that had been identified during previous HRSC events. The results of HRSC pre-bioremediation implementation sampling suggested that the TCE source area was larger than originally identified during initial site characterization activities, leading to a design refinement to improve electron donor distribution and increase the likelihood of achieving remedial objectives. Approach/Activities: HRSC was conducted from 2009 through 2014 to delineate the vertical and horizontal extent of chlorinated volatile organic compounds (CVOCs) in the groundwater. Approximately 2,340 samples were collected from 363 locations using direct push technology (DPT) groundwater sampling techniques. Samples were collected from up to 14 depth intervals at each location using a 4-foot sampling screen. This HRSC approach identified a narrow (approx. 5 to 30 feet wide), approximately 3,000 square foot TCE DNAPL source area (maximum detected TCE concentration of 160,000 micrograms per liter [micro-g/L] at DPT sampling location DPT0225). Prior to implementation of a bioremediation interim measure, HRSC baseline sampling was conducted using DPT groundwater sampling techniques. Concentrations of TCE were an order of magnitude lower than previous reported (12,000 micro-g/L maximum at DPT sampling location DPT0225) at locations sampled adjacent to previous sampling locations. To further evaluate the variability in concentrations observed additional sampling was conducted in 2016. The results identified higher concentrations than originally detected within the previously defined source area and the presence of source zone concentrations upgradient of the previously defined source area (maximum concentration observed 570,000 micro-g/L). The HRSC baseline sampling data allowed for a revision of the bioremediation design prior to implementation. Bioremediation was implemented within the eastern portion of the source area in November and December 2016 and quarterly performance monitoring was completed in March and June 2017. Reductions in CVOC concentrations from baseline were observed at all performance monitoring wells in the treatment area, and by June 2017, an approximate 95% CVOC mass reduction was observed based on monitoring well sampling results. Results/Lessons Learned: The results of this project suggest that, due to the complexity of DNAPL source zones, HRSC during pre-implementation baseline sampling in the TCE source zone was an essential strategy for verifying the treatment area and depth prior to remedy implementation. If the upgradient source zone mass was not identified prior to bioremediation implementation, the mass would have served as a long-term source for the dissolved plume.

Chrest, Anne↗
NASA NTRS2012

Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager

Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.

Keymeulen, Didlier↗
NASA NTRS2023

Space Networking Implementation for Lunar Operations

The High-Rate Delay Tolerant Networking (HDTN) project at NASA has developed a performance optimized and open-source Delay Tolerant Networking (DTN) implementation. The primary goal is to create a scalable networking solution to increase the scientific data return rate of space missions. To reach this goal, HDTN must span multiple edge cases in space networking by including tools and configurations to accommodate a wide range of space systems. Typically, HDTN evaluations are conducted on a laboratory emulation test bed, made up of hardware accelerated x86 based systems capable of data rates over 10 Gbps. HDTN must have an effective implementation process on a wide range of systems to increase the sustainability of the design. One important implementation option is with low-level embedded systems which could be used on small robotic missions. This paper details the implementation process, benchmark testing, and performance results of HDTN in multiple configurations on Raspberry Pi 4 devices. By implementing HDTN on a Raspberry Pi 4, a process for building HDTN onto ARM processors was developed and utilized to conduct benchmark tests in multiple network configurations, achieving a data rate performance exceeding 600 Mbps. Based on these results, HDTN proved to run on small ARM based systems with slight modifications to the build procedure. These results were then extended to evaluating an implementation of the HDTN software parsed across several Raspberry Pi 4 nodes. To test this capability, HDTN was configured in a simplified cut-through setup and distributed among multiple Raspberry Pi 4 processors. This distributed architecture was benchmark tested in a similar fashion to the testing of a singular HDTN implementation. The results from the benchmark testing are used to examine how these implementation options and capabilities can expand the use cases for DTN, and particularly with small robotic missions.

Space Networking↗
NASA NTRS2009

Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space

On-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A modified form of the algorithm that is better suited for data from pushbroom instruments is generally appropriate for flight implementation. A scalable field programmable gate array (FPGA) hardware implementation was developed. The FPGA implementation achieves a throughput performance of 58 Msamples/sec, which can be increased to over 100 Msamples/sec in a parallel implementation that uses twice the hardware resources This paper describes the hardware implementation of the 'Modified Fast Lossless' compression algorithm on an FPGA. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for space applications.

FPGA implementation↗