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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Explicit robust schemes for implementation of a class of principal value-based constitutive models: Symbolic and numeric implementation

The issue of developing effective and robust schemes to implement a class of the Ogden-type hyperelastic constitutive models is addressed. To this end, special purpose functions (running under MACSYMA) are developed for the symbolic derivation, evaluation, and automatic FORTRAN code generation of explicit expressions for the corresponding stress function and material tangent stiffness tensors. These explicit forms are valid over the entire deformation range, since the singularities resulting from repeated principal-stretch values have been theoretically removed. The required computational algorithms are outlined, and the resulting FORTRAN computer code is presented.

Arnold, S. M.↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS2018

Know Your Enemy - Implementation of Bioremediation within a Suspected DNAPL Source Zone Following High-Resolution Site Characterization at Contractors Road Heavy Equipment Area, Kennedy Space Center, Florida

The National Aeronautics and Space Administration (NASA), Kennedy Space Center (KSC), has adopted high-resolution site characterization (HRSC) sampling techniques during baseline sampling prior to implementation of remedies to confirm and refine the conceptual site model (CSM). HRSC sampling was performed at Contractors Road Heavy Equipment Area (CRHE) prior to bioremediation implementation to verify the extent of the trichloroethene (TCE) dense non-aqueous phase liquid (DNAPL) source area (defined as the area with TCE concentrations above 1% solubility) and its daughter product dissolved plume that had been identified during previous HRSC events. The results of HRSC pre-bioremediation implementation sampling suggested that the TCE source area was larger than originally identified during initial site characterization activities, leading to a design refinement to improve electron donor distribution and increase the likelihood of achieving remedial objectives. Approach/Activities: HRSC was conducted from 2009 through 2014 to delineate the vertical and horizontal extent of chlorinated volatile organic compounds (CVOCs) in the groundwater. Approximately 2,340 samples were collected from 363 locations using direct push technology (DPT) groundwater sampling techniques. Samples were collected from up to 14 depth intervals at each location using a 4-foot sampling screen. This HRSC approach identified a narrow (approx. 5 to 30 feet wide), approximately 3,000 square foot TCE DNAPL source area (maximum detected TCE concentration of 160,000 micrograms per liter [micro-g/L] at DPT sampling location DPT0225). Prior to implementation of a bioremediation interim measure, HRSC baseline sampling was conducted using DPT groundwater sampling techniques. Concentrations of TCE were an order of magnitude lower than previous reported (12,000 micro-g/L maximum at DPT sampling location DPT0225) at locations sampled adjacent to previous sampling locations. To further evaluate the variability in concentrations observed additional sampling was conducted in 2016. The results identified higher concentrations than originally detected within the previously defined source area and the presence of source zone concentrations upgradient of the previously defined source area (maximum concentration observed 570,000 micro-g/L). The HRSC baseline sampling data allowed for a revision of the bioremediation design prior to implementation. Bioremediation was implemented within the eastern portion of the source area in November and December 2016 and quarterly performance monitoring was completed in March and June 2017. Reductions in CVOC concentrations from baseline were observed at all performance monitoring wells in the treatment area, and by June 2017, an approximate 95% CVOC mass reduction was observed based on monitoring well sampling results. Results/Lessons Learned: The results of this project suggest that, due to the complexity of DNAPL source zones, HRSC during pre-implementation baseline sampling in the TCE source zone was an essential strategy for verifying the treatment area and depth prior to remedy implementation. If the upgradient source zone mass was not identified prior to bioremediation implementation, the mass would have served as a long-term source for the dissolved plume.

Chrest, Anne↗
NASA NTRS2012

Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager

Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.

Keymeulen, Didlier↗
NASA NTRS2023

Space Networking Implementation for Lunar Operations

The High-Rate Delay Tolerant Networking (HDTN) project at NASA has developed a performance optimized and open-source Delay Tolerant Networking (DTN) implementation. The primary goal is to create a scalable networking solution to increase the scientific data return rate of space missions. To reach this goal, HDTN must span multiple edge cases in space networking by including tools and configurations to accommodate a wide range of space systems. Typically, HDTN evaluations are conducted on a laboratory emulation test bed, made up of hardware accelerated x86 based systems capable of data rates over 10 Gbps. HDTN must have an effective implementation process on a wide range of systems to increase the sustainability of the design. One important implementation option is with low-level embedded systems which could be used on small robotic missions. This paper details the implementation process, benchmark testing, and performance results of HDTN in multiple configurations on Raspberry Pi 4 devices. By implementing HDTN on a Raspberry Pi 4, a process for building HDTN onto ARM processors was developed and utilized to conduct benchmark tests in multiple network configurations, achieving a data rate performance exceeding 600 Mbps. Based on these results, HDTN proved to run on small ARM based systems with slight modifications to the build procedure. These results were then extended to evaluating an implementation of the HDTN software parsed across several Raspberry Pi 4 nodes. To test this capability, HDTN was configured in a simplified cut-through setup and distributed among multiple Raspberry Pi 4 processors. This distributed architecture was benchmark tested in a similar fashion to the testing of a singular HDTN implementation. The results from the benchmark testing are used to examine how these implementation options and capabilities can expand the use cases for DTN, and particularly with small robotic missions.

Space Networking↗
NASA NTRS2009

Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space

On-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A modified form of the algorithm that is better suited for data from pushbroom instruments is generally appropriate for flight implementation. A scalable field programmable gate array (FPGA) hardware implementation was developed. The FPGA implementation achieves a throughput performance of 58 Msamples/sec, which can be increased to over 100 Msamples/sec in a parallel implementation that uses twice the hardware resources This paper describes the hardware implementation of the 'Modified Fast Lossless' compression algorithm on an FPGA. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for space applications.

FPGA implementation↗
NASA NTRS1994

Toward fidelity between specification and implementation

This paper describes the methods used to specify and implement a complex communications protocol that provides reliable delivery of data in multicast-capable, packet-switching telecommunication networks. The protocol, called the Reliable Multicasting Protocol (RMP), was developed incrementally by two complementary teams using a combination of formal and informal techniques in an attempt to ensure the correctness of the protocol implementation. The first team, called the Design team, initially specified protocol requirements using a variant of SCR requirements tables and implemented a prototype solution. The second team, called the V&V team, developed a state model based on the requirements tables and derived test cases from these tables to exercise the implementation. In a series of iterative steps, the Design team added new functionality to the implementation while the V&V team kept the state model in fidelity with the implementation through testing. Test cases derived from state transition paths in the formal model formed the dialogue between teams during development and served as the vehicles for keeping the model and implementation in fidelity with each other. This paper describes our experiences in developing our process model, details of our approach, and some example problems found during the development of RMP.

Callahan, John R.↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗
NASA NTRS2011

Interplanetary Overlay Network Bundle Protocol Implementation

The Interplanetary Overlay Network (ION) system's BP package, an implementation of the Delay-Tolerant Networking (DTN) Bundle Protocol (BP) and supporting services, has been specifically designed to be suitable for use on deep-space robotic vehicles. Although the ION BP implementation is unique in its use of zero-copy objects for high performance, and in its use of resource-sensitive rate control, it is fully interoperable with other implementations of the BP specification (Internet RFC 5050). The ION BP implementation is built using the same software infrastructure that underlies the implementation of the CCSDS (Consultative Committee for Space Data Systems) File Delivery Protocol (CFDP) built into the flight software of Deep Impact. It is designed to minimize resource consumption, while maximizing operational robustness. For example, no dynamic allocation of system memory is required. Like all the other ION packages, ION's BP implementation is designed to port readily between Linux and Solaris (for easy development and for ground system operations) and VxWorks (for flight systems operations). The exact same source code is exercised in both environments. Initially included in the ION BP implementations are the following: libraries of functions used in constructing bundle forwarders and convergence-layer (CL) input and output adapters; a simple prototype bundle forwarder and associated CL adapters designed to run over an IPbased local area network; administrative tools for managing a simple DTN infrastructure built from these components; a background daemon process that silently destroys bundles whose time-to-live intervals have expired; a library of functions exposed to applications, enabling them to issue and receive data encapsulated in DTN bundles; and some simple applications that can be used for system checkout and benchmarking.

Burleigh, Scott C.↗
NASA NTRS2018

Implementation of J-A Methodology Elastic-Plastic Crack Instability Analysis Capability into the WARP-3D Code

Characterization of the near crack-tip stress/strain fields is the foundation of fracture mechanics. The description of the near tip stress field and the prediction of when fracture occurs is well established for brittle materials that exhibit linear elastic behavior. However, in ductile materials or conditions that violate linear elastic assumptions (Aluminum alloys, Al 2024-T3, Al 2024- T351 etc.), the elastic-plastic crack-tip stress fields are characterized by the Hutchison-Rice-Rosengren (HRR) field. The J-integral is commonly used to characterize amplitude of the HRR field under elastic-plastic conditions. The J-integral has been demonstrated for crack-tip fields that are under high constraint conditions (i.e., small-scale plasticity where the J-dominance is maintained). However, as the external load increases, yielding changes from small- to largescale plasticity and usually a loss of constraint (i.e., reduction in the triaxial stress field along the crack front). The loss of constraint leads to the deviation of the crack-tip stress fields from that given by the HRR field. Hence, the J-dominance will be gradually lost and additional parameter(s) are required to quantify the crack-tip stress fields and predict fracture behavior. The assessment objectives were to: 1) implement a two-parameter (i.e., J-A) fracture criterion into an elastic-plastic three-dimensional (3D) finite element analysis (FEA), 2) validate the implementation by comparison with the A parameter from literature data, 3) conduct material characterization tests to quantify the material behavior and provide fracture data for validation of the J-A fracture criteria, and (4) perform evaluations to establish if the J-A criteria can be used to predict fracture in a ductile metallic material (e.g., aluminum alloys). The A parameter in these criteria is the second parameter in a three-term elastic-plastic asymptotic expansion of the neartip stress behavior. A series of extensive FEAs were performed using WARP3D software package to obtain solutions for the A parameter for different specimen configurations. The methodology needed for the estimation of the A parameter in the asymptotic expansion was developed and implemented using Matlab®. A user material (UMAT) routine was used to model the material stress-strain response using a Ramberg-Osgood power law with a hardening exponent (n) and a material coefficient (alpha). This UMAT routine was successfully implemented in WARP3D software and validated through comparison with the experimental data. Three configurations were extracted from published results: 1) center cracked plate (CCP), 2) single edge-cracked plate (SECP), and 3) double edge-cracked plate (DECP). These configurations and four other configurations (three-hole tension (THT)), three-point bend (3PTB), three-hole compact tension (3PCT), and compact tension (CT)) were analyzed to verify the methodology that was developed and implemented into WARP3D. Solutions of the A parameter were obtained for remote tension loading conditions that started with small-scale yielding and continued into the large-scale plasticity regime. The results indicate that the methodology developed can be used to calculate the elastic-plastic J-A parameters for test specimens with a range of crack geometries, material strain hardening behaviors, and loading conditions. The J-A parameters were implemented as fracture criteria and used to predict the test results. For comparison, other fracture criteria were used to predict the same test results. Major findings include: The A constraint parameter A varies with specimen type and applied load thus accurate determination is crucial in predicting the failure load, and the A parameter is asymptotic as the failure load is approached, making an accurate determination difficult (i.e., small differences in the A parameter can cause large variations in failure load) for materials exhibiting elastic-plastic behavior. The failure predictions from J-A methodology were more accurate than the traditionally used KC and J methods, and have comparable scatter to that observed when using the crack-tip opening angle (CTOA) method. However, the J-A methodology requires considerable effort (expertise level and labor) to implement and to evaluate the A parameter for different specimen types and materials, or to apply this methodology to part-through crack (e.g., 3D problems) structural applications.

Hamm, Kenneth R., Jr.↗
NASA NTRSDate not supplied

Implementation of Human Systems Integration Technical and Management Process for the Lunar Gateway Program

NASA recognizes Human Systems Integration (HSI) as part of the overall systems engineering and acquisition strategy for space systems. The Lunar Gateway Program is implementing HSI technical and management process across the lifecycle of the mission, as required by NPR 7123.1C NASA Systems Engineering Processes and Requirements, and led by the Gateway HSI team as required by NPR 8705.2C Human-Rating Requirements for Space Systems, now HEOMD-003 Crewed Deep Space Systems Human Rating Certification Requirements and Standards for NASA Missions. NASA has been using HSI principles for many years and has applied them to many of its previous human spaceflight Programs. As NASA returns to the Moon in a more sustainable manner, the Gateway Program is maturing the application of HSI by implementing it more visibly as part of Artemis, with guidance from the NASA/SP-20210010952 NASA HSI Handbook. This paper discusses how HSI is being implemented in the Gateway Program, challenges faced with its implementation during the development phase, and strategies/approaches used to overcome those. The paper also covers HSI implementation for flight systems, vehicle processing, and interfaces across the six identified NASA HSI Domains: human factors engineering, operations, safety, training, maintainability and supportability, habitability and environment. The goal is to provide an overview of the implementation process of HSI in the Gateway Program as an example for other Programs/Projects/Missionsthat are looking to implement HSI.

Jackelynne Silva-Martinez↗
NASA NTRSDate not supplied

Implementing JEDI into NASA GMAO’s Real Time Production Suite

NASA’s Global Modeling and Assimilation Office (GMAO) has prepared their first production system involving the Joint Effort for Data assimilation Integration (JEDI) framework. In this system the central analysis, that drives the deterministic forecast, will be provided using JEDI. This talk outlines the phased approach to implementing JEDI into production that GMAO has designed, and how this approach will allow for a careful analysis of the system against the existing data assimilation framework (GSI). In the first phase of implementation the existing data assimilation system will perform certain actions that are still under development in JEDI. These include thinning the observations and producing satellite bias correction coefficients. JEDI is hooked up to the existing workflow so a single line switch can activate whether the existing or JEDI-based analysis is cycled. Outside of the monumental effort to construct JEDI that is ongoing at the Joint Center for Satellite Data Assimilation (JCSDA), GMAO have undertaken two areas of considerable effort. The talk will describe these efforts and highlight the main challenges that have been encountered. The first area of work is to implement the background error model from the existing data assimilation system into JEDI. The second is to validate the observing system in JEDI against the one in GSI, which has involved several new features being added to the observation operators in JEDI. While the longer-term plans involve trying to improve on the GSI in these two areas, GMAO is keen to have JEDI start from a trusted baseline. This is also key to implementing JEDI quickly so other priorities, such as increasing the number of model levels, can be easily worked on in parallel. GMAO is actively working on a framework to shepherd in the next generation coupled data assimilation system and model. As JEDI is implemented for the first time the plan is to ambitiously cycle through implementations, frequently bringing JEDI features to production. Details of these plans will be given in the talk and we will highlight key implementation and product milestones that we hope to achieve, as well as touch on the development environment that we will use to support frequent refreshing of the production system.

JEDI↗