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An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
Modern electrical components are susceptible to damage from high levels of radiation and extreme temperatures found near reactors in terrestrial nuclear power plants and in aerospace applications. Radiation-hardened electronics are being developed, largely for the aerospace industry, but they sometimes rely on application-specific, small-batch semiconductor fabrication processes. These processes tend to be prohibitively expensive to develop and maintain outside major industrial facilities or governmental agencies. Recently, commercially available, nonradiation-rated junction-gate field-effect transistors (JFETs) were shown to maintain their functionality at gamma doses exceeding 1 MGy, suggesting that nonrated, commercially available electrical components could be used to develop systems that are tolerant to ionizing radiation. However, gamma ray survival is not indicative of neutron dose survival, and few studies characterize JFETs under neutron irradiation. To address this knowledge gap, a JFET-based analog multiplexer and optical pulsewidth modulation (PWM) encoder was developed and irradiated using a 252 Cf source to 1.6×10 13 n/cm 2 . The multiplexed optical encoder (MOE) system maintained functionality throughout testing and showed little evidence of radiation effects. These results indicate that circuitry tolerant to fast neutron damage can be developed using low-cost, nonradiation-rated, commercially available JFETs, which could provide a lower production cost alternative to specialized semiconductor processes when designing and building electronics better able to survive neutron irradiation.
Dry cask storage is one of two storage methods approved by the U.S. Nuclear Regulatory Commission for spent fuel after removal from reactor cores. Dry casks consist of a stainless steel canister enclosed in a concrete overpack to contain the hazardous radioactive spent fuel rods and provide radiation shielding. Monitoring spent fuel storage casks is desired to ensure the safe containment of the enclosed spent fuel, but is very difficult due to the related harsh temperature and radiation environment. The sensors and associated electronics to monitor temperature, pressure, and/or radiation need to survive high temperatures and radiation doses for extended time periods. For this reason, there is a severe need for radiation-hardened electrical systems that survive well beyond the existing capabilities of commercially available radiation-rated electronic components, which have primarily been developed for space applications. Junction-gate field-effect transistor (JFET) devices are inherently radiation hardened [exceeding 100 Mrad (Si)]. Additionally, when JFETs are used as building blocks for sensing and communication electronics (i.e., oscillators, amplifiers, filters, and mixers), inherently radiation-hardened circuits can be achieved. To this end, JFET-based radiation-hardened electronics interfacing with cask-embedded sensors capable of driving modulated sensor signals through a stainless steel barrier were designed and tested at a dose rate of approximately 500 krad/h (Si) to beyond a 200-Mrad (Si) total ionizing dose. After 200 Mrad (Si), the sensor and communication circuit signals were correctly decoded at the receiver despite oscillator drift. The results from this experiment demonstrate the potential for creating more complex radiation-hardened JFET-based electrical systems for nuclear environments.
Tetra Corporation is developing a pulsed power drilling system for the geothermal industry. The system requires a high temperature switching technology to replace the existing technology based on Si thyristors with a temperature limit of 150 degrees C. This work focuses on the development of such switch based on a Supercascode configuration using SiC JFET technology. The development presented contains thermal models, packaging design and processes, circuit simulations and prototypes of both the Supercascode switch and the high temperature packaged SiC JFETs.
Abstract Selective area doping in GaN, especially p-type, is a critical and inevitable building block for the realization of advanced device structures for high-power applications, including, but not limited to, current-aperture vertical electron transistors, junction termination extensions, junction barrier Schottky diodes, junction field-effect transistors (JFETs), vertical-channel JFETs, U-shaped metal–oxide–semiconductor field-effect transistors (U-MOSFETs), and Fin MOSFETs. This paper reviews and summarizes some of the recent advances in the fields of selective area etching and regrowth, ion implantation, and polarity-dependent doping that may lead to the practical realization of GaN-based power devices.
Gallium Nitride (GaN) has a great potential in high-power and high-frequency applications due to its wide energy gap and good transport property. So far all commercial GaN optoelectronic and electronic devices have planar junctions and heterostructures prepared by epitaxial growth. To take the advantage of the merits of GaN material properties, more sophisticated device configurations such as current-aperture vertical electron transistors (CAVETs), junction field-effect transistors (JFETs), and super-junction (SJ) devices require the ability to form in-plane, lateral junctions by selective area doping (SAD). In this project, we explored a novel approach of realizing SAD through selective-area etching (SAE) followed by selective-area growth (SAG).
The landscape of power transmission and distribution is quickly evolving as more power conversion is done through power electronics and transmitted or distributed at medium voltage direct current (MVDC). As power electronics tend to store less energy and be less resilient to faults than conventional power transformers, a reliable and fast protection against faults is critical to protect power electronics (PE) based infrastructure, especially for medium- and high-voltage applications. This motivates the development of PE based protection circuits to replace slower contemporary electromechanical breakers. In this project a novel PE based MVDC circuit breaker is developed; the new design is comprised of 1) a normally-on leg made of commercially-available, cascaded SiC junction field effect transistors (JFETs) with a passive balancing network, and 2) a normally-off leg based on an optically-triggered gallium nitride (GaN) photoconductive semiconductor switch (PCSS). The normally-off leg was designed to be quickly turned on, to divert current to an auxiliary dissipative circuit, as the normally-on leg is turned off. This approach, using solid-state devices, was selected for a high-performance, fast-switching operation for the DC circuit breaker as compared to approaches that use slower mechanical switches. To be practical, the circuit breaker must have low conduction loss (low Ron) in the normally-on leg and fast coordinated triggering of the normally-off leg to avoid damage from inductive flyback, which could be considerable for long lengths of cable.
4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.
A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.