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An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.
Modern electrical components are susceptible to damage from high levels of radiation and extreme temperatures found near reactors in terrestrial nuclear power plants and in aerospace applications. Radiation-hardened electronics are being developed, largely for the aerospace industry, but they sometimes rely on application-specific, small-batch semiconductor fabrication processes. These processes tend to be prohibitively expensive to develop and maintain outside major industrial facilities or governmental agencies. Recently, commercially available, nonradiation-rated junction-gate field-effect transistors (JFETs) were shown to maintain their functionality at gamma doses exceeding 1 MGy, suggesting that nonrated, commercially available electrical components could be used to develop systems that are tolerant to ionizing radiation. However, gamma ray survival is not indicative of neutron dose survival, and few studies characterize JFETs under neutron irradiation. To address this knowledge gap, a JFET-based analog multiplexer and optical pulsewidth modulation (PWM) encoder was developed and irradiated using a 252 Cf source to 1.6×10 13 n/cm 2 . The multiplexed optical encoder (MOE) system maintained functionality throughout testing and showed little evidence of radiation effects. These results indicate that circuitry tolerant to fast neutron damage can be developed using low-cost, nonradiation-rated, commercially available JFETs, which could provide a lower production cost alternative to specialized semiconductor processes when designing and building electronics better able to survive neutron irradiation.
Dry cask storage is one of two storage methods approved by the U.S. Nuclear Regulatory Commission for spent fuel after removal from reactor cores. Dry casks consist of a stainless steel canister enclosed in a concrete overpack to contain the hazardous radioactive spent fuel rods and provide radiation shielding. Monitoring spent fuel storage casks is desired to ensure the safe containment of the enclosed spent fuel, but is very difficult due to the related harsh temperature and radiation environment. The sensors and associated electronics to monitor temperature, pressure, and/or radiation need to survive high temperatures and radiation doses for extended time periods. For this reason, there is a severe need for radiation-hardened electrical systems that survive well beyond the existing capabilities of commercially available radiation-rated electronic components, which have primarily been developed for space applications. Junction-gate field-effect transistor (JFET) devices are inherently radiation hardened [exceeding 100 Mrad (Si)]. Additionally, when JFETs are used as building blocks for sensing and communication electronics (i.e., oscillators, amplifiers, filters, and mixers), inherently radiation-hardened circuits can be achieved. To this end, JFET-based radiation-hardened electronics interfacing with cask-embedded sensors capable of driving modulated sensor signals through a stainless steel barrier were designed and tested at a dose rate of approximately 500 krad/h (Si) to beyond a 200-Mrad (Si) total ionizing dose. After 200 Mrad (Si), the sensor and communication circuit signals were correctly decoded at the receiver despite oscillator drift. The results from this experiment demonstrate the potential for creating more complex radiation-hardened JFET-based electrical systems for nuclear environments.
In the future ATLAS Inner Tracker, each silicon strip module will be equipped with a switch able to separate the high voltage supply from the sensor in case the latter becomes faulty. The switch, placed in between the HV supply and the sensor, needs to sustain a high voltage in its OFF state, to offer a low resistance path for the sensor leakage current in the ON state, and be radiation hard up to 1.2 * 10 15 neq/cm 2 along with other requirements. While GaN JFETs have been selected as suitable rad-hard switch, a silicon vertical HV-JFET was developed by Brookhaven National Laboratory as an alternative option. Pre-irradiation results showed the functionality of the device and proved that the silicon HV-JFET satisfied the pre-irradiation requirements for the switch. To assess its suitability after irradiation, a few p-type HV-JFETs have been neutron irradiated at Jozef Stefan Institute (JSI, Ljubljana, Slovenia). Overall, this paper reports the static characterization of these irradiated devices and the TCAD numerical simulations used to get an insight of the physics governing the post-irradiation behaviour.
Tetra Corporation is developing a pulsed power drilling system for the geothermal industry. The system requires a high temperature switching technology to replace the existing technology based on Si thyristors with a temperature limit of 150 degrees C. This work focuses on the development of such switch based on a Supercascode configuration using SiC JFET technology. The development presented contains thermal models, packaging design and processes, circuit simulations and prototypes of both the Supercascode switch and the high temperature packaged SiC JFETs.
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A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
Abstract Selective area doping in GaN, especially p-type, is a critical and inevitable building block for the realization of advanced device structures for high-power applications, including, but not limited to, current-aperture vertical electron transistors, junction termination extensions, junction barrier Schottky diodes, junction field-effect transistors (JFETs), vertical-channel JFETs, U-shaped metal–oxide–semiconductor field-effect transistors (U-MOSFETs), and Fin MOSFETs. This paper reviews and summarizes some of the recent advances in the fields of selective area etching and regrowth, ion implantation, and polarity-dependent doping that may lead to the practical realization of GaN-based power devices.
To assist the US Department of Energy in defining a course for Office of Nuclear Energy–funded radiation-hardened (rad-hard) electronics research, Oak Ridge National Laboratory (ORNL) will focus on three main tasks in FY21. The first task will investigate the survivability of silicon junction-gate field-effect transistors (Si-JFETs) through a 100 Mrad total ionizing dose (TID) experiment and report the test results. The second task will investigate wide bandgap (WBG)-based JFET devices and sources. The third task is an investigation into commercially available systems and components and will be performed to determine whether a standardized list of devices can be identified for reactor instrumentation application. If the devices are feasible, then this list will provide direction to designers and equipment suppliers for selection of components to meet specific reactor requirements.
Gallium Nitride (GaN) has a great potential in high-power and high-frequency applications due to its wide energy gap and good transport property. So far all commercial GaN optoelectronic and electronic devices have planar junctions and heterostructures prepared by epitaxial growth. To take the advantage of the merits of GaN material properties, more sophisticated device configurations such as current-aperture vertical electron transistors (CAVETs), junction field-effect transistors (JFETs), and super-junction (SJ) devices require the ability to form in-plane, lateral junctions by selective area doping (SAD). In this project, we explored a novel approach of realizing SAD through selective-area etching (SAE) followed by selective-area growth (SAG).