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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

AnalyzeThat: A Programmable Shared-Memory System for an Array of Processing-In-Memory Devices

Processing In Memory (PIM), the concept of integrating processing directly with memory, has been attracting a lot of attention since PIM can assist in overcoming the throughput limitation caused by data movement between CPU and memory. The challenge, however, is that it requires the programmers to have a deep understanding of the PIM architecture to maximize the benefits such as data locality and parallel thread execution on multiple PIM devices. In this study, we present AnalyzeThat, a programmable shared-memory system for parallel data processing with PIM devices. Thematic to AnalyzeThat is a rich PIM-Aware Data Structure (PADS), which is an encapsulation that integrally ties together the data, the analysis tasks and the runtime needed to interface with the PIM device array. The PADS abstraction provides (i) a key-value data container that allows programmers to easily store data on multiple PIMs, (ii) a suite of parallel operations with which users can easily implement data analysis applications, and (iii) a runtime, hidden to programmers, which provides the mechanisms needed to overlay both the data and the tasks on the PIM device array in an intelligent fashion, based on PIM-specific information collected from the hardware. We have developed a PIM emulation framework called AnalyzeThat. Our experimental evaluation with representative data analytics applications suggests that the proposed system can significantly reduce the PIM programming effort without losing its technology benefits.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Photo‐/Thermal‐Responsive Field‐Effect Transistor upon Blending Polymeric Semiconductor with Hexaarylbiimidazole toward Photonically Programmable and Thermally Erasable Memory Device

Abstract It is shown that the semiconducting performance of field‐effect transistors (FETs) with PDPP4T (poly(diketopyrrolopyrrole‐quaterthiophene)) can be reversibly tuned by UV light irradiation and thermal heating after blending with the photochromic hexaarylbiimidazole compound ( p ‐NO 2 ‐HABI). A photo‐/thermal‐responsive FET with a blend thin film of PDPP4T and p ‐NO 2 ‐HABI is successfully fabricated. The transfer characteristics are altered significantly with current enhanced up to 10 6 ‐fold at V G = 0 V after UV light irradiation. However, further heating results in the recovery of the transfer curve. This approach can be extended to other semiconducting polymers such as P3HT (poly(3‐hexyl thiophene)), PBTTT (poly(2,5‐bis(3‐tetradecylthiophen‐2‐yl)thieno[3,2‐b] thiophene)) and PDPPDTT (poly(diketopyrrolopyrrole‐dithienothiophene)). It is hypothesized that TPIRs (2,4,5‐triphenylimidazolyl radicals) formed from p ‐NO 2 ‐HABI after UV light irradiation can interact with charge defects at the gate dielectric–semiconductor interface and those in the semiconducting layer to induce more hole carriers in the semiconducting channel. The application of the blend thin film of PDPP4T and p ‐NO 2 ‐HABI is further demonstrated to fabricate the photonically programmable and thermally erasable FET‐based nonvolatile memory devices that are advantageous in terms of i) high ON/OFF current ratio, ii) nondestructive reading at low electrical bias, and iii) reasonably highly stable ON‐state and OFF‐state.

Liu, Yidong↗
DOE OSTI2017

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator

Resistive memory (ReRAM) shows promise for use as an analog synapse element in energy-efficient neural network algorithm accelerators. A particularly important application is the training of neural networks, as this is the most computationally-intensive procedure in using a neural algorithm. However, training a network with analog ReRAM synapses can significantly reduce the accuracy at the algorithm level. In order to assess this degradation, analog properties of ReRAM devices were measured and hand-written digit recognition accuracy was modeled for the training using backpropagation. Bipolar filamentary devices utilizing three material systems were measured and compared: one oxygen vacancy system, Ta-TaO x , and two conducting metallization systems, Cu-SiO 2 , and Ag/chalcogenide. Analog properties and conductance ranges of the devices are optimized by measuring the response to varying voltage pulse characteristics. Key analog device properties which degrade the accuracy are update linearity and write noise. Write noise may improve as a function of device manufacturing maturity, but write nonlinearity appears relatively consistent among the different device material systems and is found to be the most significant factor affecting accuracy. As a result, this suggests that new materials and/or fundamentally different resistive switching mechanisms may be required to improve device linearity and achieve higher algorithm training accuracy.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Systems and methods for shock-resistant memory devices

A shock-resistant memory device comprises a housing and a memory module. The memory module is disposed within the housing and surrounded by potting material to protect the memory module from damage during a shock event. The housing can include a port that accommodates a data connection between the memory module and a sensor from which data is desirably received by the memory module. During a shock event the connection between the memory module and the sensor may be severed, but data stored in the memory module can be retained in the memory module which is protected by the housing. To facilitate retrieval of the memory device subsequent to a shock event, a balloon can be affixed to the housing. The balloon can be configured to inflate subsequent to the shock event so that the shock-resistant memory device does not sink in water and to make the memory device more visible for recovery.

42 ENGINEERING↗
DOE OSTI2021

GASNet-EX Memory Kinds: Support for Device Memory in PGAS Programming Models

There is an emerging need for adaptive, lightweight communication in irregular HPC applications at exascale, where GPU accelerators provide the majority of available compute cycles. To address this need, Lawrence Berkeley National Lab is developing a programming system to support distributed-memory HPC application development using the Partitioned Global Address Space (PGAS) model. This work includes two major components: UPC++ and GASNet-EX. UPC++ is a C++ template library providing Remote Memory Access (RMA) and Remote Procedure Call (RPC) communication interfaces. GASNet-EX is a portable, high-performance communication middleware library, used by the implementations of UPC++ and many other PGAS programming models. We describe recent advances in GASNet-EX to efficiently implement zero-copy Remote Memory Access (RMA) communication to and from memory on accelerator devices such as GPUs. We demonstrate performance improvements via benchmark results from UPC++ (on Summit) and the Legion programming system (on DGX-1), both using GASNet-EX for communication.

Hargrove, Paul H↗
DOE OSTI2018

Bidirectional shape memory device

A resistively heated shape memory polymer device is operated using resistive heating to heat the shape memory polymer device. The resistively heated shape memory polymer device is made by providing a wire that includes a resistive medium. The wire is coated with a first shape memory polymer. The wire is exposed and electrical leads are attached to the wire. In one embodiment the shape memory polymer device is in the form of a clot destruction device. In another embodiment the shape memory polymer device is in the form of a microvalve. In another embodiment the shape memory polymer device is in the form of a micropump. In yet another embodiment the shape memory polymer device is in the form of a thermostat or relay switch.

36 MATERIALS SCIENCE↗
DOE OSTI2018

Bidirectional shape memory device

A resistively heated shape memory polymer device is operated using resistive heating to heat the shape memory polymer device. The resistively heated shape memory polymer device is made by providing a wire that includes a resistive medium. The wire is coated with a first shape memory polymer. The wire is exposed and electrical leads are attached to the wire. In one embodiment the shape memory polymer device is in the form of a clot destruction device. In another embodiment the shape memory polymer device is in the form of a microvalve. In another embodiment the shape memory polymer device is in the form of a micropump. In yet another embodiment the shape memory polymer device is in the form of a thermostat or relay switch.

Marion, III, John E.↗
DOE OSTI2016

Enhanced oxygen vacancy diffusion in Ta{sub 2}O{sub 5} resistive memory devices due to infinitely adaptive crystal structure

Metal oxide resistive memory devices based on Ta{sub 2}O{sub 5} have demonstrated high switching speed, long endurance, and low set voltage. However, the physical origin of this improved performance is still unclear. Ta{sub 2}O{sub 5} is an important archetype of a class of materials that possess an adaptive crystal structure that can respond easily to the presence of defects. Using first principles nudged elastic band calculations, we show that this adaptive crystal structure leads to low energy barriers for in-plane diffusion of oxygen vacancies in λ phase Ta{sub 2}O{sub 5}. Identified diffusion paths are associated with collective motion of neighboring atoms. The overall vacancy diffusion is anisotropic with higher diffusion barriers found for oxygen vacancy movement between Ta-O planes. Coupled with the fact that oxygen vacancy formation energy in Ta{sub 2}O{sub 5} is relatively small, our calculated low diffusion barriers can help explain the low set voltage in Ta{sub 2}O{sub 5} based resistive memory devices. Our work shows that other oxides with adaptive crystal structures could serve as potential candidates for resistive random access memory devices. We also discuss some general characteristics for ideal resistive RAM oxides that could be used in future computational material searches.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Development of Conjugated Polymers for Memory Device Applications

This review summarizes the most widely used mechanisms in memory devices based on conjugated polymers, such as charge transfer, space charge traps, and filament conduction. In addition, recent studies of conjugated polymers for memory device applications are also reviewed, discussed, and differentiated based on the mechanisms and structural design. Moreover, the electrical conditions of conjugated polymers can be further fine-tuned by careful design and synthesis based on the switching mechanisms. The review also emphasizes and demonstrates the structure-memory properties relationship of donor-acceptor conjugated polymers for advanced memory device applications.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Nanometer scale nonvolatile memory device and method for storing binary and quantum memory states

Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe2) crystals onto the BN bottom layer to form a metallic layer, depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer, and depositing the graphite crystals onto the BN top layer to form a gate top layer.

Xiao, Jun↗
DOE OSTI2017

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (≤30 ns), excellent endurance (~10 12 cycles), stability (>10 6 s) and scalability (down to ~60 nm 2 ). In situ Raman and ultraviolet–visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Goswami, Sreetosh↗
DOE OSTI2018

A programmable shared-memory system for an array of processing-in-memory devices

Processing in memory (PIM), the concept of integrating processing directly with memory has been attracting a lot of attention, since PIM can assist in overcoming the throughput limitation caused by data movement between CPU and memory. The challenge, however, is that it requires the programmers to have a deep understanding of the PIM architecture to maximize the benefits such as data locality and parallel thread execution on multiple PIM devices. In this study, we present AnalyzeThat, a programmable shared-memory system for parallel data processing with PIM devices. Thematic to AnalyzeThat is a rich PIM-aware data structure (PADS), which is an encapsulation that integrally ties together the data, the analysis tasks and the runtime needed to interface with the PIM device array. The PADS abstraction provides (i) a sophisticated key-value data container that allows programmers to easily store data on multiple PIMs, (ii) a suite of parallel operations with which users can easily implement data analysis applications, and (iii) a runtime, hidden to programmers, which provides the mechanisms needed to overlay both the data and the tasks on the PIM device array in an intelligent fashion, based on PIM-specific information collected from the hardware. We have developed a PIM emulation framework called AnalyzeThat. In conclusion, our experimental evaluation with representative data analytics applications suggests that the proposed system can significantly reduce the PIM programming effort without losing its technology benefits.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Bias control for a memory device

Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Bias control for a memory device

Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Walker, Dean↗
DOE OSTI2018

2D nanocomposite of hexagonal boron nitride nanoflakes and molybdenum disulfide quantum dots applied as the functional layer of all-printed flexible memory device

Highlights: • We have proposed a flexible, rewritable and NVM device based on an advanced 2D nanocomposite. • 2D nanocomposite is synthesized by mixing hBN flakes and MoS{sub 2} QDs. • Entire device was fabricated through extremely simple and highly controllable printing technology. • The RRAM device was tested electrically, mechanically, thermally and chemically. - Abstract: In this study, we have proposed a flexible, rewritable and nonvolatile memory device based on an advanced 2D nanocomposite of hexagonal boron nitride (hBN) flakes and molybdenum disulfide quantum dots (MoS{sub 2} QDs). Complete device fabrication was carried out by using extremely simple and highly controllable all printed technology. The electrical characteristics exhibited by the as developed memory devices included the switching ratio, electrical endurance and retention time of ∼10{sup 3}, 10{sup 3} and 10{sup 4} respectively. The device turned ON and OFF at the SET and RESET threshold voltages of +1.4 V and −1 V respectively. The obtained results of electrical and thermal characterizations exhibited that the switching ratio decreases via either increasing temperature (300 K–380 K) or device size (42 μm–100 μm) hence verifying the formation of conductive filament through the functional layer. Moreover, no major degradation in the switching characteristics was observed even after 1500 bending cycles.

77 NANOSCIENCE AND NANOTECHNOLOGY↗