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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

Hall, William A.↗
NASA NTRS1988

Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

Rogers, David↗
NASA NTRS1989

A Cerebellar-model Associative Memory as a Generalized Random-access Memory

A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

Kanerva, Pentti↗
DOE OSTI2025

JACC.shared: Leveraging HPC Metaprogramming and Performance Portability for Computations That Use Shared Memory GPUs

In this work, we present JACC.shared, a new feature of Julia for ACCelerators (JACC), which is the performanceportable and metaprogramming model of the just-in-time and LLVM-based Julia language. This new feature allows JACC applications to leverage the high-performance computing (HPC) capabilities of high-bandwidth, on-chip GPU memory. Historically, exploiting high-bandwidth, shared-memory GPUs has not been a priority for high-level programming solutions. JACC.shared covers that gap for the first time, thereby providing a highlevel, portable, and easy-to-use solution for programmers to exploit this memory and supporting all current major accelerator architectures. Well-known HPC and AI workloads, such as multi/hyperspectral imaging and AI convolutions, have been used to evaluate JACC.shared on two exascale GPU architectures hosted by some of the most powerful US Department of Energy supercomputers: Perlmutter (NVIDIA A100) and Frontier (AMD MI250X). The performance evaluation reports speedup of up to 3.5× by adding only one line of code to the base codes, thus providing important accelerators in a simple, portable, and transparent way and elevating the programming productivity and performance-portability capabilities for Julia/JACC HPC, AI, and scientific applications.

Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗
NASA NTRS1986

Analysis of memory use for improved design and compile-time allocation of local memory

Trace analysis techniques are used to study memory referencing behavior for the purpose of designing local memories and determining how to allocate them for data and instructions. In an attempt to assess the inherent behavior of the source code, the trace analysis system described here reduced the effects of the compiler and host architecture on the trace by using a technical called flattening. The variables in the trace, their associated single-assignment values, and references are histogrammed on the basis of various parameters describing memory referencing behavior. Bounds are developed specifying the amount of memory space required to store all live values in a particular histogram class. The reduction achieved in main memory traffic by allocating local memory is specified for each class.

Mcniven, Geoffrey D.↗
NASA NTRS1989

A general model for memory interference in a multiprocessor system with memory hierarchy

The problem of memory interference in a multiprocessor system with a hierarchy of shared buses and memories is addressed. The behavior of the processors is represented by a sequence of memory requests with each followed by a determined amount of processing time. A statistical queuing network model for determining the extent of memory interference in multiprocessor systems with clusters of memory hierarchies is presented. The performance of the system is measured by the expected number of busy memory clusters. The results of the analytic model are compared with simulation results, and the correlation between them is found to be very high.

Taha, Badie A.↗
NASA NTRS1989

Recoverable distributed shared virtual memory - Memory coherence and storage structures

This paper examines the problem of implementing rollback recovery in multicomputer distributed shared virtual memory environments, in which the shared memory is implemented in software and exists only virtually. A user-transparent checkpointing recovery scheme and new twin-page disk storage management are presented to implement a recoverable distributed shared virtual memory. The checkpointing scheme is integrated with the shared virtual memory management. The twin-page disk approach allows incremental checkpointing without an explicit undo at the time of recovery. A single consistent checkpoint state is maintained on stable disk storage. The recoverable distributed shared virtual memory allows the system to restart computation from a previous checkpoint due to a processor failure without a global restart.

Wu, Kun-Lung↗
NASA NTRS1972

Optical memory development. Volume 1: prototype memory system

The design, development, and implementation of a prototype, partially populated, million bit read-write holographic memory system using state-of-the-art components are described. The system employs an argon ion laser, acoustooptic beam deflectors, a holographic beam splitter (hololens), a nematic liquid crystal page composer, a photoconductor-thermoplastic erasable storage medium, a silicon P-I-N photodiode array, with lenses and electronics of both conventional and custom design. Operation of the prototype memory system was successfully demonstrated. Careful attention is given to the analysis from which the design criteria were developed. Specifications for the major components are listed, along with the details of their construction and performance. The primary conclusion resulting from this program is that the basic principles of read-write holographic memory system are well understood and are reducible to practice.

Cosentino, L. S.↗
NASA NTRS1993

A ground-based memory state tracker for satellite on-board computer memory

The TOPEX/POSEIDON satellite, currently in Earth orbit, will use radar altimetry to measure sea surface height over 90 percent of the world's ice-free oceans. In combination with a precise determination of the spacecraft orbit, the altimetry data will provide maps of ocean topography, which will be used to calculate the speed and direction of ocean currents worldwide. NASA's Jet Propulsion Laboratory (JPL) has primary responsibility for mission operations for TOPEX/POSEIDON. Software applications have been developed to automate mission operations tasks. This paper describes one of these applications, the Memory State Tracker, which allows the ground analyst to examine and track the contents of satellite on-board computer memory quickly and efficiently, in a human-readable format, without having to receive the data directly from the spacecraft. This process is accomplished by maintaining a groundbased mirror-image of spacecraft On-board Computer memory.

Quan, Alan↗
NASA NTRS2002

Performance Evaluation of Remote Memory Access (RMA) Programming on Shared Memory Parallel Computers

The purpose of this study is to evaluate the feasibility of remote memory access (RMA) programming on shared memory parallel computers. We discuss different RMA based implementations of selected CFD application benchmark kernels and compare them to corresponding message passing based codes. For the message-passing implementation we use MPI point-to-point and global communication routines. For the RMA based approach we consider two different libraries supporting this programming model. One is a shared memory parallelization library (SMPlib) developed at NASA Ames, the other is the MPI-2 extensions to the MPI Standard. We give timing comparisons for the different implementation strategies and discuss the performance.

Jin, Hao-Qiang↗
NASA NTRS2010

Memories and NASA Spacecraft: A Description of Memories, Radiation Failure Modes, and System Design Considerations

As NASA has evolved it's usage of spaceflight computing, memory applications have followed as well. In this slide presentation, the history of NASA's memories from magnetic core and tape recorders to current semiconductor approaches is discussed. There is a brief description of current functional memory usage in NASA space systems followed by a description of potential radiation-induced failure modes along with considerations for reliable system design.

LaBel, Kenneth A.↗
NASA NTRS2010

Improvement in the Shape Memory Response of Ti50.5Ni24.5Pd25 High-Temperature Shape Memory Alloy with Scandium Microalloying

A Ti(50.5)Ni(24.5)Pd25 high-temperature shape memory alloy (HTSMA) is microalloyed with 0.5 at. pct scandium (Sc) to enhance its shape-memory characteristics, in particular, dimensional stability under repeated thermomechanical cycles. For both Ti(50.5)Ni(24.5)Pd25 and the Sc-alloyed material, differential scanning calorimetry is conducted for multiple cycles to characterize cyclic stability of the transformation temperatures. The microstructure is evaluated using electron microscopy, X-ray diffractometry, and wavelength dispersive spectroscopy. Isobaric thermal cycling experiments are used to determine transformation temperatures, dimensional stability, and work output as a function of stress. The Sc-doped alloy displays more stable shape memory response with smaller irrecoverable strain and narrower thermal hysteresis than the baseline ternary alloy. This improvement in performance is attributed to the solid solution hardening effect of Sc.

Atli, K. C.↗
NASA NTRS2011

Shape Memory Characteristics of Ti(sub 49.5)Ni(sub 25)Pd(sub 25)Sc(sub 0.5) High-Temperature Shape Memory Alloy After Severe Plastic Deformation

A Ti(49.5)Ni25Pd25Sc(0.5) high-temperature shape memory alloy is thermomechanically processed to obtain enhanced shape-memory characteristics: in particular, dimensional stability upon repeated thermal cycles under constant loads. This is accomplished using severe plastic deformation via equal channel angular extrusion (ECAE) and post-processing annealing heat treatments. The results of the thermomechanical experiments reveal that the processed materials display enhanced shape memory response, exhibiting higher recoverable transformation and reduced irrecoverable strain levels upon thermal cycling compared with the unprocessed material. This improvement is attributed to the increased strength and resistance of the material against defect generation upon phase transformation as a result of the microstructural refinement due to the ECAE process, as supported by the electron microscopy observations.

Atli, K. C.↗
NASA NTRS1976

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Besser, P. J.↗
NASA NTRS1984

Simulations for Full Unit-memory and Partial Unit-memory Convolutional Codes with Real-time Minimal-byte-error Probability Decoding Algorithm

A program which was written to simulate Real Time Minimal-Byte-Error Probability (RTMBEP) decoding of full unit-memory (FUM) convolutional codes on a 3-bit quantized AWGN channel is described. This program was used to compute the symbol-error probability of FUM codes and to determine the signal to noise (SNR) required to achieve a bit error rate (BER) of 10 to the minus 6th power for corresponding concatenated systems. A (6,6/30) FUM code, 6-bit Reed-Solomon code combination was found to achieve the required BER at a SNR of 1.886 dB. The RTMBEP algorithm was then modified for decoding partial unit-memory (PUM) convolutional codes. A simulation program was also written to simulate the symbol-error probability of these codes.

Vo, Q. D.↗
DOE OSTI2025

ScaWL: Scaling k-WL (Weisfeiler-Lehman) Algorithms in Memory and Performance on Shared and Distributed-Memory Systems

The k-dimensional Weisfeiler-Lehman (k-WL) algorithm—developed as an efficient heuristic for testing if two graphs are isomorphic—is a fundamental kernel for node embedding in the emerging field of graph neural networks. Unfortunately, the k-WL algorithm has exponential storage requirements, limiting the size of graphs that can be handled. This work presents a novel k-WL scheme with a storage requirement orders of magnitude lower while maintaining the same accuracy as the original k-WL algorithm. Due to the reduced storage requirement, our scheme allows for processing much bigger graphs than previously possible on a single compute node. For even bigger graphs, we provide the first distributed-memory implementation. Our k-WL scheme also has significantly reduced communication volume and offers high scalability. Our experimental results demonstrate that our approach is significantly faster and has superior scalability compared to five other implementations employing state-of-the-art techniques.

algorithims↗