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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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14 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Micro-mechanical investigation of the thermo-mechanical properties of micro-architectured tungsten coatings

The thermo-mechanical response of micro-architectured tungsten coatings is characterized in the temperature range of 293 to 673 K using both in situ micro-compression experiments inside a scanning electron microscope (SEM) as well as image-based crystal plasticity finite element method (CPFEM) simulations. The experiments were conducted on micropillar-like specimens that were focus ion beam milled into the coatings, while the simulations were conducted on columnar-grained micropillar simulation cells constructed based on the statistics of the coating’s microstructure. The experimental results show that the stress–strain response and deformation mode exhibit a strong temperature-dependence. At room temperature, catastrophic failure is observed shortly after yield and is manifested in the form of intergranular fracture and buckling of individual columnar grains. With increasing temperature, this catastrophic failure is gradually suppressed and the material exhibits a steadier strain hardening response at 693 K. The CPFEM simulations are also shown to be in good agreement with the experimental results, and these simulations indicate that the material response is strongly influenced by the local crystallographic anisotropy and microstructure inhomogeneity. Furthermore, the simulations capture the underlying mechanisms that control the temperature-dependent transition in deformation mode. The current results highlight that the micro-architectured microstructure offers a great combination of excellent mechanical strength and structural integrity at elevated temperatures, which is of importance for high temperature applications.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Revolutionizing Turbine Cooling with Micro-Architectures Enabled by Direct Metal Laser Sintering

The objective of this research effort was to explore innovative cooling architectures enabled by additive manufacturing techniques for improved turbine cooling performance. The ability to create complex internal geometries was leveraged to better distribute coolant as well as to integrate inherently unstable flow devices to enhance internal and external heat transfer. This was accomplished with a multi-faceted approach including analytical, experimental, and computational components. This final report documents progress during the total 4.25 year effort that was extended (at no additional cost) from the original 3-year cooperative agreement. Prior to starting the project, significant effort was invested in investigating innovative cooling designs from the open literature. When the project started, we quickly down-selected to 4 configurations: impingement jet fluidic oscillators (for internal leading edge cooling), reverse film cooling (for pressure surface), sweeping film cooling jets (for suction surface), and trailing edge slot cooling with microchannels. During the 2nd year, the reverse film cooling design was shown to be sub-optimal and work on that topic was halted. The three remaining technologies were integrated into a large scale nozzle guide vane and installed into a low-speed linear cascade facility for further interrogation. Initial results showed the sweeping film cooling jets (on the suction surface) to be the most promising technology compared to a baseline diffusion shaped film hole (777 design). The benefit was particularly evident at high blowing ratios (>1.5) when the 777 coolant film separated from the downstream surface. Benefits were also evident at elevated freestream turbulence levels. The leading edge cooling with unsteady jets was less effective in terms of peak or average cooling – however it was superior to round hole impingement cooling in terms of spatial uniformity. Finally, the trailing edge cooling design with micro-channels was scrapped in favor of a pinned arrangement with centerbody. During the 3rd year, the same three technologies were integrated into a transonic linear cascade for an assessment of compressibility effects. Again, the sweeping film cooling jets proved superior at high blowing ratios while the unsteady leading edge impingement and trailing edge pin-fins with centerbody designs yielded mixed results. Finally, during the 4th and final year, these 3 technologies were integrated into a direct metal laser sintered (DMLS) nozzle guide vane for testing in a high temperature, transonic annular vane cascade. The facility matches the flow temperature, Mach number, and coolant pressure ratios of an actual gas turbine. Before doing this, an additional series of tests were completed to validate a redesigned trailing edge cooling architecture. This final design included a centerbody with triangular pins between the centerbody and the vane external skin. The majority of these triangular pins are fabricated with a 30% gap to the centerbody – reducing their pressure drop considerably while still providing excellent heat transfer augmentation. This additional test campaign required an additional 3-month extension request to complete testing in the high temperature NGV test facility (Turbine Reacting Flow Rig – TuRFR). Testing of the DMLS vane in TuRFR pitted the 3 innovative cooling technologies against more traditional technologies (shaped 777 film hole, round impingement jet, and full pin arrangement in the trailing edge. The sweeping film cooling jets (on the suction surface) showed approximately 15% improvement in overall effectiveness compared to the 777 film hole while the trailing edge showed up to 20% improvement. The leading edge impingement was disappointing with a substantially lower effectiveness than traditional direct impingement. In summary, the study was successful in demonstrating that DMLS-enabled cooling technologies can yield significant gains in cooling performance.

03 NATURAL GAS↗
DOE OSTI2022

MAPredict: Static Analysis Driven Memory Access Prediction Framework for Modern CPUs

Application memory access patterns are crucial in deciding how much traffic is served by the cache and forwarded to the dynamic random-access memory (DRAM). However, predicting such memory traffic is difficult because of the interplay of prefetchers, compilers, parallel execution, and innovations in manufacturer-specific micro-architectures. This research introduced MAPredict, a static analysis-driven framework that addresses these challenges to predict last-level cache (LLC)-DRAM traffic. By exploring and analyzing the behavior of modern Intel processors, MAPredict formulates cache-aware analytical models. MAPredict invokes these models to predict LLC-DRAM traffic by combining the application model, machine model, and user-provided hints to capture dynamic information. MAPredict successfully predicts LLC-DRAM traffic for different regular access patterns and provides the means to combine static and empirical observations for irregular access patterns. Evaluating 130 workloads from six applications on recent Intel micro-architectures, MAPredict yielded an average accuracy of 99% for streaming, 91% for strided, and 92% for stencil patterns. By coupling static and empirical methods, up to 97% average accuracy was obtained for random access patterns on different micro-architectures.

Monil, M. A. H.↗
DOE OSTI2022

Anisotropic yield models for lattice unit cell structures exploiting orthotropic symmetry

We report numerical homogenization enables efficient computational analysis and design of multiscale structures made of micro-architected materials including lattice unit cells. However, predicting yield is nontrivial because it requires accurate and efficient predictions of the maximum stress inside the homogenized unit cells. To address this challenge, we develop a macroscale anisotropic yield function for micro-architected materials. The yield function depends on the three-dimensional macroscale stress state and the parameters describing a family of micro-architectures, such as the radii of the struts in a lattice unit cell. To ensure accuracy, we determine the maximum stress using three-dimensional continuum finite-element analysis. To ensure efficiency, we construct surrogate models from the aforementioned high-fidelity results for yield prediction. To reduce simulation costs and surrogate modeling complexity, we leverage orthotropic symmetry commonly found in lattice unit cells. In this paper, we provide a thorough presentation of group representations and the systematic procedure to exploit orthotropic domain symmetry in homogenization and surrogate modeling. We illustrate the use of linear homogenization results to predict yield in specific unit cells without further simulations. We furthermore show that surrogate modeling presents a viable option for anisotropic yield prediction in a continuously parametrized family of micro-architectures. More specifically, despite the dimensionality and degree of nonlinearity in the maximum micro von Mises stress within the unit cell, the surrogate models can predict it with less than 5% error at least 90% of the time. Moreover, the largest under-prediction error, which is more critical than the over-prediction error, is typically less than 10%.

42 ENGINEERING↗
DOE OSTI2020

Selective-Area Remote Epitaxy of ZnO Microrods Using Multilayer–Monolayer-Patterned Graphene for Transferable and Flexible Device Fabrications

Here, selective-area remote epitaxy (SA-REpi) is demonstrated for fabricating mechanically releasable position-controlled ZnO microrod (MR) arrays from donor wafers in an arrayed form. Intaglio-patterned graphene, consisting of basal single-layer graphene (SLG) overlayered with multilayer graphene (MLG) patterned with perforated holes, is transferred onto a GaN/Al 2 O 3 wafer on which the hydrothermal synthesis is performed for growing ZnO MRs. The basal SLG area exposed through the MLG pattern yields ZnO MRs, whereas the MLG plateau inhibits the growth. The noncovalent remote epitaxial heterointerface enables the release of the MR overlayer in the arrayed form, and the original source wafer is refurbished for reproducibly repeating the SA-REpi. Density-functional theory calculations suggest that localized surface charge density is induced on the surface of SLG by the underlying GaN across ultrathin SLG, which possibly provides a driving force for precursor adatoms and the following remote epitaxy of ZnO. In contrast, the induction of the charge density redistribution does not clearly occur through MLG; so, that keeps the surface of MLG nearly charge-neutral. The diameter and spacing of ZnO MRs are controlled in a designed way by changing the pattern geometries. High-resolution scanning transmission electron microscopy reveals the remote heteroepitaxial relationship at an atomic level. The remote epitaxy is expected to provide an ideal platform to transfer the addressable spatial arrays of nano- or micro-architecture semiconductor components to arbitrary target surfaces directly after the growth without the assembly procedures.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Structural Simluation Toolkit (SST) v.12.0

The Structural Simulation Toolkit (SST) was developed to explore innovations in highly concurrent computing systems where the instruction set architecture (ISA), micro-architecture, and memory interact with the programming model and communications system. The package provides a fully modular design for extensive exploration of an individual system parameter as well as a parallel simulation environment based on message passing interface (MPI) which enable a high level of performance as well as the ability to look at large systems. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Rodrigues, ArunF.↗
DOE OSTI2025

If We Build Them, They Will Run: Automated HPC Apps Deployment and Profiling with eBPF in Cloud

The high performance computing (HPC) community is in a period of transition. The rise of AI/ML coupled with a changing landscape of resources deems portability a new metric of performance, and methods to move between on-premises and cloud environments and assess compatibility are paramount. Here we design and test a strategy for bridging the gap between traditional HPC and Kubernetes environments – first containerizing applications, providing automated orchestration to run studies, and packaging the setup with automated means to assess performance using low overhead eXtended Berkeley Packet Filter (eBPF) programs. We first assess different designs for eBPF collection, demonstrating a tradeoff between number of programs deployed on a node and overhead added. We develop 5 low overhead eBPF programs that combine with streaming ML models to assess CPU, futex, TCP, shared memory, and file access across four different builds of an HPC application for CPU and GPU. We use eBPF data to generate insights into the possible underlying etiology of scaling issues. We then assess compatibility of a well-known benchmark, HPCG, across matrices of micro-architectures and optimization levels (217 containers across 24 instance types and over 7500 runs). We provide to the community 30 applications to deploy in our automated setup and perform a scaling study from 4 to a maximum of 256 nodes for both CPU and GPU applications. Finally, we use our gained knowledge about performance to generate compatibility artifacts that are used by a newly developed Kubernetes controller to intelligently select instance type based on optimizing a figure of merit. Along with insights to scaling in this environment with a collection of applications and templates to work from, we provide an overall strategy for approaching HPC application deployment and image selection based on compatibility in cloud.

Computer science↗
DOE OSTI2026

Micro-architected material design for mechanical response

Rapid advances in additive manufacturing (AM) have enabled the creation of micro-architected materials—also known as mechanical metamaterials—with unprecedented control over fine-scale geometries and arrangements of multiple material constituents. These “materials” can achieve unique and extraordinary effective mechanical properties through their complex architectures rather than composition alone. A key challenge is to design for these bespoke effective mechanical responses within the constraints of available AM techniques (i.e., given a set of desired effective properties), identify a (often nonunique) micro-architecture and selection of material constituents that achieves them. Two main strategies have emerged. Gradient-based methods use sensitivity analysis to iteratively refine candidate designs, while data-driven methods learn micro-architecture-constituent relationships from existing examples to propose new designs. This article reviews these design approaches for micro-architected materials with tailored mechanical responses that can be fabricated by AM as well as their applications.

Spadaccini, Christopher M [Lawrence Livermore Nati↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
DOE OSTI2021

Enabling Design Space Exploration for RISC-V Secure Compute Environments

Cycle-level architectural simulation of Trusted Execution Environments (TEEs) can enable extensive design space exploration of these secure architectures. Existing architectural simulators which support TEEs are either based on hardware-level implementations or abstract analytic models. In this paper, we describe the implementation of the gem5 models necessary to run and evaluate the RISC- V-based open source TEE, Keystone, and we discuss how this simulation environment opens new avenues for designing and studying these trusted environments. We show that the Keystone simulations on gem5 exhibit similar performance as the previous hardware evaluations of Keystone. We also describe three simple example use cases (understanding the reason of trusted execution slowdown, performance of memory encryption, and micro-architecture impact on trusted execution performance) to demonstrate how the ability to simulate TEEs can provide useful information about their behavior in the existing form and also with enhanced designs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

FPGA-Accelerated Range-Limited Molecular Dynamics

Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. Finally, the potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.

97 MATHEMATICS AND COMPUTING↗