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Increasing Multilayer Ceramic Capacitor Lifetime With Bipolar Voltage Cycling

Enhancing the lifetime of multilayer ceramic capacitors (MLCCs) is critical in many aerospace, naval, or electrical grid applications, where device failure could lead to catastrophic consequences. The migration of oxygen vacancies from the ceramic to the electrode interface under constant bias is known to reduce the lifetime of oxide-based MLCCs. Bias cycling presents an opportunity to enhance MLCC lifetime by reducing oxygen vacancy migration. The ideal frequency range is expected to lie between frequencies low enough to avoid self-heating but high enough to avoid interfacial defect formation. However, the impact of low-frequency bipolar voltage cycling (BVC) on MLCC degradation mechanisms has not been well studied. This work investigates the impact of periodic BVC on the degradation of MLCCs through highly accelerated lifetime testing (HALT) on X7R capacitors. HALT tests were conducted at 255 °C and 60 V using different switching frequencies: 0 (dc), 0.1, 2.5, and 10 Hz. BVC was found to improve the lifetime of MLCCs compared to dc test conditions. MLCCs tested at 10-Hz BVC showed a 311% increase in average time to failure compared to the dc case. Impedance spectroscopy shows that BVC decreases the rate of resistance degradation within MLCCs, indicating that oxygen vacancy migration to the electrodes is mitigated. The impedance spectra taken on BVC samples highlight how grain boundaries play a vital role in trapping oxygen vacancies. Periodic cycling causes oxygen vacancies to become trapped at grain boundaries, resulting in oxygen vacancies taking longer to reach the electrode interface and thus increasing MLCC lifetime. This work highlights not only how BVC can be used to increase MLCC lifetime but also how periodically cycling MLCCs could increase lifetime in extreme environments, such as at elevated temperatures and electric fields.

Chuong, Kayla Y.

Correcting impedance measurements for background parasitics to characterize circuit components in cryogenic environments

Predictable circuit response is a critical prerequisite for accurate electronic measurements. Here, we describe a powerful yet straightforward experimental method and analysis model that utilizes an affordable LCR meter in conjunction with an in situ parasitic-impedance background-correction procedure to measure the temperature-dependent impedance (magnitude and phase) of up to ten individual passive circuit elements in a single cryostat run. We show how the model unambiguously identified a ∼20× drop in capacitance for 22 μF 5XR multilayer ceramic capacitors cooled from 300 K to 360 mK in an environment with a parasitic capacitance of ∼300 pF. The same experimental procedure, based on a simple two-wire measurement, was also used to measure 10 and 22 pF thin-film capacitors and 100 MΩ thick-film resistors. The results showed that the resistor values increased by up to an order of magnitude when the devices were cooled from 300 K to 360 mK. Most importantly, we showed that the simple data-acquisition method, coupled with our analysis model, enabled the measurement of component parasitics, and effectively extended the accuracy of a commercial LCR meter beyond its manufacturer-guaranteed values for a wide range of measurement frequencies. We also showed that, in the current configuration, our simple approach is limited to a capacitance accuracy of ∼10 pF.

Carpenter, R. J. [Santa Clara Univ., Santa Clara,

Nucleation and growth of polar clusters with in-phase tilts into a long-range ferroelectric matrix in a sodium niobate based complex relaxor

In this study, we have investigated the temperature dependence of atomic ordering at multiple length scales in a lead-free sodium niobate-based relaxor, i.e., 0.75 NaNbO 3 -0.25 Ba 0.9⁢ Ca 0.1⁢ TiO 3 (NN-25BCT) via synchrotron x-ray diffraction, Raman spectroscopy, and pair distribution function analysis. High-resolution synchrotron x-ray powder diffraction (SXRD) measurements reveal a ferroelectric phase transition in the relaxor ferroelectric NN-25BCT below the Vogel-Fulcher freezing temperature (𝑇 VF ≈ 270 K). In addition, SXRD analysis demonstrates the competition between in-phase octahedral tilting and ferroelectric order at the long-range scale using mode crystallography. On the other hand, Raman spectroscopic analysis provides evidence of polar ordering for 𝑇 > 𝑇 VF (with tetragonal symmetry) persisting up to the Burns temperature (𝑇 B ). Furthermore, pair distribution function (PDF) analysis reveals the presence of a polar antiferrodistortive tetragonal phase with 𝑃⁢4⁢𝑏𝑚 space group at short ranges throughout the studied temperatures (i.e., 110 K ≤ 𝑇 ≤500 K), irrespective of nonpolar long-range ordering above 𝑇 VF . Therefore, our measurements provide direct evidence for the presence of polar ordering at short ranges and their gradual transformation into long-range polar ordering using an integrated multiscale structural analysis. In conclusion, as a result of a transition from relaxor to a ferroelectric phase in the vicinity of room temperature, NN-25BCT can be exploited for applications in pyroelectric detectors, electrocaloric devices, and multilayered ceramic capacitors.

36 MATERIALS SCIENCE

Novel ceramic capacitors with ultrahigh energy density and efficiency (Final Technical Report)

Antiferroelectric ceramics are a special class of material that have shown great potential as the dielectric in electrical capacitors due to their high energy- and power-density. During each charge-discharge cycle, the ceramic undergoes transformation to a ferroelectric phase and resumes its antiferroelectric phase. The hysteresis associated with the transitions leads to a mediocre energy efficiency and service lifetime of antiferroelectric capacitors and, hence, their almost absence in commercial products. Under the support of this research project, we first formulated a universal lattice-compatibility theory that included electrostatic polarization energy along with elastic energy and thermal energy to understand the origin of the hysteresis in antiferroelectric oxides. Guided by this compatibility theory, we conducted high-throughput density functional theory (DFT) calculations to assess chemical modifiers and their effect on crystal structures of 400+ PbZrO 3 -based compositions. Down-selected compositions were experimentally validated for their suppressed hysteresis and higher energy efficiency. The verified low-hysteresis compositions were then expanded to an antiferroelectric ceramic library with nearly 500 new compositions (more than 1,500 samples) using high-throughput experiments involving ceramic synthesis and property screening. The large quantity of data generated (theory and experimental) in these tasks were processed by machine-learning techniques and identified trends were fed to the next iteration. In the end, we successfully discovered four compositions with near-zero hysteresis, yielding a world-record energy efficiency of 98.2% at an energy density of 3.0 J/cm 3 . Furthermore, our antiferroelectric ceramic capacitor reaches 79.5 million charge-discharge cycles lifetime, a factor of 80 enhancement over previous antiferroelectric ceramics with large hysteresis. These research accomplishments have not only met the milestones set in the SOPO, but also led to two patent filings, three journal publications (one of them was in Advanced Materials, impact factor 29.4), and nine oral presentations at various venues. Through the course of the project, three postdocs, four Ph.D. students, and one M.S. student were trained. In short, our project established a new methodology in searching next-generation functional ceramics on the fundamental side and discovered several high-efficiency antiferroelectric compositions for capacitors on the applied side. Once fabricated into the multilayer form for commercial applications, these ceramic capacitors can potentially enable the high temperature high power density DC-link capacitors that are critical for the next generation inverters in electric vehicles. The project also significantly contributed to the nation’s workforce development in the STEM fields.

36 MATERIALS SCIENCE

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro