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Contents include the following: PCB design with HDL designer, design process and schematic capture - symbols and diagrams: 1. Motivation: time savings, money savings, simplicity. 2. Approach: use single tool PCB for FPGA design, more FPGA designs than PCB designers. 3. Use HDL designer for schematic capture.
In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.
Computing capabilities of space systems have in-creased onboard performance by orders of magnitude with the use of radiation-tolerant field-programmable gate arrays (FPGA)and processors. The incorporation of signal and power integrity analysis with printed circuit board (PCB) design in reliable computing architectures for space systems has become critical to enable future mission capabilities. Developers launch high-performance processors into a breadth of orbits and missions, running varying applications that create challenges for designing reliable computing hardware. Specifically, for these designs, academic and industry research has focused on component radiation performance, fault mitigation, and reliable architectures. How-ever, other design parameters including electromagnetic interference (EMI), PCB stackup, signal integrity (SI), voltage regulator module (VRM) design, and power distribution network (PDN)are often deprioritized or disregarded as the design matures. Since these characteristics are becoming more significant in high-performance processor designs, this research presents a hardware design and analysis methodology for high-performance, space-computing systems that focuses on a holistic design approach and PDN reliability. While these challenges exist across all space hardware, the reduced PCB dimensions imposed by SmallSats and CubeSats introduce additional hurdles, specifically to VRM and decoupling design. By examining the relationship between the PDN and radiation performance, an analytical relationship is developed that incorporates Total Ionizing Dose and Single-Event Transients to ensure reliability throughout the mission duration. The presented design methodology is applied to the SpaceCube v3.0 Mini, an FPGA-based on-board science data processing system developed at NASA Goddard Space Flight Center.
This paper presents the results of an experiment designed to determine the effectiveness of adopting several low-noise printed circuit board (PCB) design practices. Two boards were designed and fabricated, each consisting of identical mixed signal circuitry. Several important differences were introduced between the board layouts: one board was constructed using recommended low-noise practices and the other constructed without such attention. The emissions from the two boards were then measured and compared, demonstrating an improvement in radiated emissions of up to 22 dB.
The exchange of Computer Aided Design (CAD) information between dissimilar CAD systems is a problem. This is especially true for transferring electronics CAD information such as multi-chip module (MCM), hybrid microcircuit assembly (HMA), and printed circuit board (PCB) designs. Currently, there exists several neutral data formats for transferring electronics CAD information. These include IGES, EDIF, and DXF formats. All these formats have limitations for use in exchanging electronic data. In an attempt to overcome these limitations, the Navy's MicroCIM program implemented a project to transfer hybrid microcircuit design information between dissimilar CAD systems. The IGES (Initial Graphics Exchange Specification) format is used since it is well established within the CAD industry. The goal of the project is to have a complete transfer of microelectronic CAD information, using IGES, without any data loss. An Application Protocol (AP) is being developed to specify how hybrid microcircuit CAD information will be represented by IGES entity constructs. The AP defines which IGES data items are appropriate for describing HMA geometry, connectivity, and processing as well as HMA material characteristics.
This document describes the instrumentation, operational theory, circuit implementation, calibration procedures, and general notes for the CIRSSE general purpose pneumatic hand. The mechanical design and the control software are discussed. The circuit design, PCB layout, hand instrumentation, and controller construction described in detail in this document are the result of a senior project.
PCB Assurance Summary: PCB assurance actives are informed by risk in context of the Project. Lessons are being applied across Projects for continuous improvements. Newer component technologies, smaller/high pitch devices: tighter and more demanding PCB designs: Identifying new research areas. New materials, designs, structures and test methods.
With the rise of additively manufactured electronics, the importance of thin, flexible printed batteries has increased for shape-conformal electronics. Traditionally, battery cells such as industry-standard lithium-ion batteries, have been rigid and therefore unable to conform to time-variant surfaces such as smart cards/RFID devices, disposable battery-powered skin patches, foldable electronic devices, and IoT nodes. Aligned with the effort to advance technologies on printed electronics for habitat systems and advanced manufacturing, this proof-of-concept will focus on printing a 50 mAh Zn-Ag battery implementing a DIW Technique. After prototype manufacturing, electrical and environmental testing on the flexible battery cell will be conducted to the evaluate energy and power density over 50 charge cycles under standard atmosphere conditions. The project aims to provide PCB designers, fabricators, and assemblers an integrated battery package to eliminate external batteries, external wiring and connectors, and conformational complexity. Potential end uses of the printed battery process will be within Martian and lunar habitat systems, Gateway, and surface vehicles, or aerial robots where space and geometry is a restriction.
The use of rigid-flex printed circuit board (PCB) as primary structure has the potential to reduce the weight and volume of robotic systems. In the case of robotics for interplanetary exploration, these systems can leverage origamiinspired folding for increased mobility options and reduced storage volume. Folding rigid-flex PCB robotics can be constructed with rigid PCB connected by short Nomex fabric hinges coupled with flex PCB ribbon cables that permits enhanced system flexibility and energy dissipation to promote impact survivability. This paper presents a design methodology of rigidflex PCB systems with an emphasis on impact resistance. The design process considers solder joint adequacy, panel bending, and fracture using a finite element (FE) model. The proposed design methodology is developed using a case study with NASA JPL’s Pop-Up Folding Flat Explorer Robot (PUFFER). First, the finite-element (FE) modeling methodology is presented with consideration to both frequency and time-domain modeling applications, which include operational self-contact analysis and high impact scenarios. The time-domain impact modeling methodology utilizes hyperelastic material properties for the Nomex hinges. This modeling method is validated using image correlation of PUFFER drop tests. A flowchart is presented to guide users through a validated Abaqus modeling procedure for highly flexible rigid-flex systems. Next, a case study is presented in which PUFFER is subject to drop heights representative of falls into Lunar pits and then the design is refined for a more optimum impact performance. Finally, the results of the case study are used to inform a generalized design methodology for rigid-flex PCB robotics subject to high-impact loads with the considerations presented.
The use of rigid-flex printed circuit board (PCB) as primary structure has the potential to reduce the weight and volume of robotic systems. In the case of robotics for interplanetary exploration, these systems can leverage origami-inspired folding for increased mobility options and reduced storage volume. Folding rigid-flex PCB robotics can be constructed with rigid PCB connected by short Nomex fabric hinges coupled with flex PCB ribbon cables that permits enhanced system flexibility and energy dissipation to promote impact survivability. This paper presents a design methodology of rigid-flex PCB systems with an emphasis on impact resistance. The design process considers solder joint adequacy, panel bending, and fracture using a finite element (FE) model. The proposed design methodology is developed using a case study with NASA JPL's Pop-Up Folding Flat Explorer Robot (PUFFER). First, the finite-element (FE) modeling methodology is presented with consideration to both frequency and time-domain modeling applications, which include operational self-contact analysis and high impact scenarios. The time-domain impact modeling methodology utilizes hyperelastic material properties for the Nomex hinges. This modeling method is validated using image correlation of PUFFER drop tests. A flowchart is presented to guide users through a validated Abaqus modeling procedure for highly flexible rigid-flex systems. Next, a case study is presented in which PUFFER is subject to drop heights representative of falls into Lunar pits and then the design is refined for a more optimum impact performance. Finally, the results of the case study are used to inform a generalized design methodology for rigid-flex PCB robotics subject to high-impact loads with the considerations presented.
For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.
For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.
For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.
The 2020 CIF funded Modular Composite Damage Detection System (MCDDS) aims to advance the technology of damage detection in composites in the areas of thin, flexible damage detection panel construction, encapsulation techniques in composite matrixes, innovative integration and interfacing techniques with flexible embedded sensory panels, repair methods of composite materials, and improved packaging of the MCDDS. Custom thin, flexible polyimide printed circuit boards (PCBs) were designed and procured for fabrication of test specimens. A custom interface PCB was designed and fabricated to monitor the newly developed damage detection test specimens. Test specimens were fabricated using the novel flexible circuitry that were either fully or partially encapsulated. The fully encapsulated specimens were used to demonstrate embedded damage detection concepts and the partially encapsulated specimens were used to demonstrate surface-mounted (laminate) damage detection concepts. The new composite damage detection test specimens were tested and evaluated to determine if the novel damage detection sensory panels could withstand low-cycle threshold fatigue loading per a modified version of American Society for Testing and Materials (ASTM) D 7264 for up to 50 cycles without void formation. The data for multiple sensory panels indicates that the newly fabricated sensory panels are robust and do indeed withstand three-point bend flexural loading for more than 50 cycles. Additionally, testing was performed to determine if damage could be detected in damage detection test specimens subjected to failure using a 3-point bend test per a modified version of ASTM D 7264. Again, multiple sensory panels (both fully and partially encapsulated) showed the ability to detect damage to specimens subjected to failure per a modified version of ASTM D 7264. Additionally, a novel concept for tracking and monitoring of cracking (and potentially delamination) in composites was designed and developed that utilizes painted-on conductors.
Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments (TI)' MSP430 16-bit ultra-low-power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display (LCD) touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320 by 240 RGB resistive color screen including an optional carrier board. The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA (Field Programmable Gate Array) development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At the moment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process. Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments’ MSP430 16 bit ultra-low power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320x240 RGB resistive color screen including an optional carrier board.The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At themoment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process.Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate school for a master's or doctorate degree in electrical or computer engineering.
Next generation 5G mobile architectures will take advantage of the millimeter-wave spectrum to deliver unprecedented bandwidth. Concurrently, there is a need to consolidate numerous disparate allocations into a single, multi-functional array. Existing arrays are either narrow-band, prohibitively expensive or cannot be scaled to these frequencies. In this paper, we present the first ultra-wideband millimeter-wave array to operate across the six 5G and ISM bands spanning 24-71 GHz. Critically, the array is realized using low-cost PCB. The design concept and optimized layout are presented, and fabrication and measurement considerations are discussed.
The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design
The Digital Beamforming Synthetic Aperture Radar (DBSAR) is an eight-channel phased array radar system that employs solid-state radar transceivers, a microstrip patch antenna, and a reconfigurable waveform generator and processor unit. The original DBSAR transceiver design utilizes connectorized electronic components that tend to be physically large and heavy. To achieve increased functionality in a smaller volume, PCB (printed circuit board) transceivers were designed to replace the large connectorized transceivers. One of the most challenging problems designing the transceivers in a PCB format was achieving proper performance in the calibration path. For a radar loop-back calibration path, a portion of the transmit signal is coupled out of the antenna feed and fed back into the receiver. This is achieved using passive components for stability and repeatability. Some signal also leaks through the receive path. As these two signal paths are correlated via an unpredictable phase, the leakage through the receive path during transmit must be 30 dB below the calibration path. For DBSAR s design, this requirement called for a 100-dB isolation in the receiver path during transmit. A total of 16 solid-state L-band transceivers on a PCB format were designed. The transceivers include frequency conversion stages, T/R switching, and a calibration path capable of measuring the transmit power-receiver gain product during transmit for pulse-by-pulse calibration or matched filtering. In particular, this calibration path achieves 100-dB isolation between the transmitted signal and the low-noise amplifier through the use of a switching network and a section of physical walls achieving attenuation of radiated leakage. The transceivers were designed in microstrip PCBs with lumped elements and individually packaged components for compactness. Each transceiver was designed on a single PCB with a custom enclosure providing interior walls and compartments to isolate transceiver subsystems from radiated interference. The enclosure also acts as a heat sink for the voltage regulators and power amplifiers inside the system. The PCB transceiver design produces transmit pulses of 2 W with an arbitrary duty cycle. Each transceiver is fed by an external 120-MHz signal transmit and two 1,140-MHz local oscillator signals. The received signal is amplified and down-converted to 120 MHz and is fed to the data processor. The transceiver dimensions are approximately 3.5 11.5 0.6 in. (9 29 1.5 cm). The PCB transceiver design reduces the volume and weight of the DBSAR instrument while maintaining the functionality found in the original design. Both volume and weight are critical for airborne and flight remote sensing instrumentation.