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NASA NTRS2013

A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

PLL Reference↗

NASA NTRS2007

Wide Tuning Capability for Spacecraft Transponders

A document presents additional information on the means of implementing a capability for wide tuning of microwave receiver and transmitter frequencies in the development reported in the immediately preceding article, VCO PLL Frequency Synthesizers for Spacecraft Transponders (NPO- 42909). The reference frequency for a PLL-based frequency synthesizer is derived from a numerically controlled oscillator (NCO) implemented in digital logic, such that almost any reference frequency can be derived from a fixed crystal reference oscillator with microhertz precision. The frequency of the NCO is adjusted to track the received signal, then used to create another NCO frequency used to synthesize the transmitted signal coherent with, and at a specified frequency ratio to, the received signal. The frequencies can be changed, even during operation, through suitable digital programming. The NCOs and the related tracking loops and coherent turnaround logic are implemented in a field-programmable gate array (FPGA). The interface between the analog microwave receiver and transmitter circuits and the FPGA includes analog-to-digital and digital-toanalog converters, the sampling rates of which are chosen to minimize spurious signals and otherwise optimize performance. Several mixers and filters are used to properly route various signals.

Lux, James↗

NASA NTRS1975

Uniform sampling analysis of a hybrid phase-locked loop with a sample-and-hold phase detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.

Barab, S.↗

NASA NTRS1971

A compilation of results pertaining to the behavior of phase locked loops

State-of-the art on phase locked loops PLL is reported by summarizing some specific results. Following a statement of the overall analysis and design objectives, results are presented in a format identifying working terminology, inherent assumptions, and references for each result. The use of PLL in tracking, synchronization, and demodulation is reemphasized, as well as the mathematical challenge involved in solving nonlinear stochastic differential equations.

Gleicher, N.↗

NASA NTRS1995

A novel photonic oscillator

We report a novel oscillator for photonic RF systems. This oscillator is capable of generating high-frequency signals up to 70 GHz in both electrical and optical domains and is a special voltage-controlled oscillator with an optical output port. It can be used to make a phase-locked loop (PLL) and perform all functions that a PLL is capable of for photonic systems. It can be synchronized to a reference source by means of optical injection locking, electrical injection locking, and PLL. It can also be self-phase locked and self-injection locked to generate a high-stability photonic RF reference. Its applications include high-frequency reference regeneration and distribution, high-gain frequency multiplication, comb-frequecy and square-wave generation, carrier recovery, and clock recovery. We anticipate that such photonic voltage-controlled oscillators (VCOs) will be as important to photonic RF systems as electrical VCOs are to electrical RF systems.

Yao, X. S.↗

NASA NTRS2004

A 2-to-48-MHz Phase-Locked Loop

A 2-to-48-MHz phase-locked loop (PLL), developed for the U.S. space program, meets or exceeds all space shuttle clock electrical interface requirements by taking as its reference a 2-to-48-MHz clock signal and outputting a phaselocked clock signal set at the same frequency as the reference clock with transistor- transistor logic (TTL) voltage levels. Because it is more adaptable than other PLLs, the new PLL can be used in industries that employ signaling devices and as a tool in future space missions. A conventional PLL consists of a phase/frequency detector, loop filter, and voltage-controlled oscillator in which each component exists individually and is integrated into a single device. PLL components phase-lock to a single frequency or to a narrow bandwidth of frequencies. It is this design, however, that prohibits them from maintaining phase lock to a dynamically changing reference clock when a large bandwidth is required a deficiency the new PLL overcomes. Since most PLL components require their voltage-controlled oscillators to operate at greater than 2-MHz frequencies, conventional PLLs often cannot achieve the low-frequency phase lock allowed by the new PLL. The 2-to-48-MHz PLL is built on a wire-wrap board with pins wired to three position jumpers; this makes changing configurations easy. It responds to variations in voltage-controlled oscillator (VCO) ranges, duty cycle, signal-to-noise ratio (SNR), amplitude, and jitter, exceeding design specifications. A consensus state machine, implemented in a VCO range detector which assures the PLL continues to operate in the correct range, is the primary control state machine for the 2-to-48-MHz PLL circuit. By using seven overlapping frequency ranges with hysteresis, the PLL output sets the resulting phase-locked clock signal at a frequency that agrees with the reference clock with TTL voltage levels. As a space-shuttle tool, the new PLL circuit takes the noisy, degraded reference clock signals as input and outputs phase-locked clock signals of the same frequency but with a corrected wave shape. Since its configuration circuit can be easily changed, the new PLL can do the following: readily respond to variations in VCO ranges, duty cycle, SNR, amplitude, and jitter; continuously operate in the correct VCO range because of its consensus state machine; and use its range detector implements to overlap seven frequency ranges with hysteresis, thus giving the current design a flexibility that exceeds anything available at the time of this development. These features will benefit any industry in which safe and timely clock signals are vital to operation.

Koudelka, Robert D.↗

NASA NTRS2009

Joint Carrier-Phase Synchronization and LDPC Decoding

A method has been proposed to increase the degree of synchronization of a radio receiver with the phase of a suppressed carrier signal modulated with a binary- phase-shift-keying (BPSK) or quaternary- phase-shift-keying (QPSK) signal representing a low-density parity-check (LDPC) code. This method is an extended version of the method described in Using LDPC Code Constraints to Aid Recovery of Symbol Timing (NPO-43112), NASA Tech Briefs, Vol. 32, No. 10 (October 2008), page 54. Both methods and the receiver architectures in which they would be implemented belong to a class of timing- recovery methods and corresponding receiver architectures characterized as pilotless in that they do not require transmission and reception of pilot signals. The proposed method calls for the use of what is known in the art as soft decision feedback to remove the modulation from a replica of the incoming signal prior to feeding this replica to a phase-locked loop (PLL) or other carrier-tracking stage in the receiver. Soft decision feedback refers to suitably processed versions of intermediate results of iterative computations involved in the LDPC decoding process. Unlike a related prior method in which hard decision feedback (the final sequence of decoded symbols) is used to remove the modulation, the proposed method does not require estimation of the decoder error probability. In a basic digital implementation of the proposed method, the incoming signal (having carrier phase theta theta (sub c) plus noise would first be converted to inphase (I) and quadrature (Q) baseband signals by mixing it with I and Q signals at the carrier frequency [wc/(2 pi)] generated by a local oscillator. The resulting demodulated signals would be processed through one-symbol-period integrate and- dump filters, the outputs of which would be sampled and held, then multiplied by a soft-decision version of the baseband modulated signal. The resulting I and Q products consist of terms proportional to the cosine and sine of the carrier phase cc as well as correlated noise components. These products would be fed as inputs to a digital PLL that would include a number-controlled oscillator (NCO), which provides an estimate of the carrier phase, theta(sub c).

Simon, Marvin↗

NASA NTRS1985

New results on the PLL false lock phenomenon

Conditions, based on the multipliers of a linear differential equation with periodic coefficients, for the occurrence of false lock in a phase lock loop (PLL) are presented. Two new and powerful algorithms are presented for computing the frequency difference between the reference and voltage controlled oscillator when the loop is false locked. The first algorithm expresses omega f sup -1 as a power series in the closed loop gain. The second algorithm expresses omega sup -1 as part of a solution to a nonlinear algebraic system of equations which can be solved by numerical methods. The power of both algorithms is illustrated by application and comparison.

Stensby, J. L.↗

NASA NTRS1981

Performance evaluation of antenna arrays with noisy carrier reference

The performance evaluation of coherent receivers with noisy carrier references and multiple antennas is presented. The received signal is assumed to be residual carrier BPSK, with a PLL used for extracting the carrier. Explicit relationships between the error probabilities and the various system parameters are given. Specific results are given for the performance gain of combined carrier referencing over baseband only combining when the channel alignment process is ideal. A simple asymptotic expression for the performance gain is determined when the number of antennas used is increased without bound. Examples using Deep Space Network receivers illustrate the performance of each arraying structure.

Yan, T. Y.↗

NASA NTRS1981

An efficient technique for the performance evaluation of antenna arrays with noisy carrier reference

An efficient computational technique is developed to evaluate the performance of coherent receivers with noisy carrier reference and multiple antennas. The received signal is assumed to be uncoded residual carrier BPSK (binary phase shift keying), with a PLL (phase locked loop) used for extracting the carrier. Explicit relationships between the error probabilities and the various system parameters are given. Specific results are given for the performance gain of combined carrier referencing over baseband only combining when the channel alignment process is ideal. A simple asymptotic expression for the performance gain is determined when the number of antennas used is increased without bound. An example using a Block 3 Deep Space Network PLL illustrates the performance of each arraying structure. The technique used is applicable to the performance evaluation for other receivers having similar decision statistics.

Yan, T. Y.↗

NASA NTRS1973

Automatic carrier acquisition system

An automatic carrier acquisition system for a phase locked loop (PLL) receiver is disclosed. It includes a local oscillator, which sweeps the receiver to tune across the carrier frequency uncertainty range until the carrier crosses the receiver IF reference. Such crossing is detected by an automatic acquisition detector. It receives the IF signal from the receiver as well as the IF reference. It includes a pair of multipliers which multiply the IF signal with the IF reference in phase and in quadrature. The outputs of the multipliers are filtered through bandpass filters and power detected. The output of the power detector has a signal dc component which is optimized with respect to the noise dc level by the selection of the time constants of the filters as a function of the sweep rate of the local oscillator.

Bunce, R. C.↗

NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗

NASA NTRS1981

Reference clock parameters for digital communications systems applications

The basic parameters relevant to the design of network timing systems describe the random and systematic time departures of the system elements, i.e., master (or reference) clocks, transmission links, and other clocks controlled over the links. The quantitative relations between these parameters were established and illustrated by means of numerical examples based on available measured data. The examples were limited to a simple PLL control system but the analysis can eventually be applied to more sophisticated systems at the cost of increased computational effort.

Kartaschoff, P.↗

NASA NTRS1985

Normalizing VFO Frequency by Non-Powr-of-2 Division

PLL oscillator with VFO operating at one frequency yields any one of four frequencies by dividing by 4, 7, 21, or 52.5. Radiation resistant phase-locked loop oscillator generates output frequency 32 times any 1 or 4 specific input reference frequencies constructed without increasing component count over that of conventional circuit.

Anderson, C. R.↗

NASA NTRS2005

Coupled Receiver/Decoders for Low-Rate Turbo Codes

been proposed for receiving weak single- channel phase-modulated radio signals bearing low-rate-turbo-coded binary data. Originally intended for use in receiving telemetry signals from distant spacecraft, the proposed receiver/ decoders may also provide enhanced reception in mobile radiotelephone systems. A radio signal of the type to which the proposal applies comprises a residual carrier signal and a phase-modulated data signal. The residual carrier signal is needed as a phase reference for demodulation as a prerequisite to decoding. Low-rate turbo codes afford high coding gains and thereby enable the extraction of data from arriving radio signals that might otherwise be too weak. In the case of a conventional receiver, if the signal-to-noise ratio (specifically, the symbol energy to one-sided noise power spectral density) of the arriving signal is below approximately 0 dB, then there may not be enough energy per symbol to enable the receiver to recover properly the carrier phase. One could solve the problem at the transmitter by diverting some power from the data signal to the residual carrier. A better solution . a coupled receiver/decoder according to the proposal . could reduce the needed amount of residual carrier power. In all that follows, it is to be understood that all processing would be digital and the incoming signals to be processed would be, more precisely, outputs of analog-to-digital converters that preprocess the residual carrier and data signals at a rate of multiple samples per symbol. The upper part of the figure depicts a conventional receiving system, in which the receiver and decoder are uncoupled, and which is also called a non-data-aided system because output data from the decoder are not used in the receiver to aid in recovering the carrier phase. The receiver tracks the carrier phase from the residual carrier signal and uses the carrier phase to wipe phase noise off the data signal. The receiver typically includes a phase-locked loop (PLL) or Costas loop that requires no delay or perhaps a single sample delay. The lower part of the figure depicts a basic coupled receiver/decoder . a data-aided system that would implement an iterative receiving/decoding process. The receiver would include a PLL or a Wiener filter that, to the extent possible, would track the residual carrier signal, wipe phase noise off the data signal, then send the result to the turbo decoder. Recovery of timing could be effected by, for example, a digital transition tracking loop (DTTL) or other, similar loop. The first iteration of turbo decoding would yield soft data symbols, which would be sent back to the receiver for use in softly wiping off the data signal in an effort to recover the residual carrier signal. The wiped signal would contain a relatively large carrier-phase component that could be tracked by use of a second Wiener filter.

Hamkins, Jon↗