Here's a DC-to-pulse-width converter.
Circuit design and performance to convert DC INPUT voltage to pulse train with width proportional to input
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Circuit design and performance to convert DC INPUT voltage to pulse train with width proportional to input
Bipolar analog-to-pulse width converter to implement analog-to-digital conversion in spacecraft systems
Infrared spacecraft horizon scanner with variable width pulse integrating circuit
Transformer-coupled output stage is used with pulse-width modulated class-D dc amplifiers. Circuit is comprised of two channels corresponding to negative and positive input signals. Amplitude of secondary-current triangular pulse is function of duration of driving pulse. Therefore, circuit converts pulse-width modulated driving signal to pulse-amplitude modulated signal.
An evolution equation in the form of a modified Korteweg-de Vries equation is developed which describes the small-amplitude version of the infinitesimal rotational discontinuity (RD) studied by Wang and Sonnerup (1984). It is shown that the small-amplitude version of the equilibrium pulse solution obtained by Wang and Sonnerup is metastable and thus unlikely to arise spontaneously. When the initial pulse amplitude is smaller than and/or the initial pulse width is greater than the equilibrium value, the pulse decays. When the reverse is the case, the pulse is converted to an infinitesimal intermediate-mode solitary wave having greater pulse amplitude and speed. A simulation experiment is performed in which one of the equilibrium intermediate-mode solitary waves overtakes another, less rapidly moving version of the same wave. The existence of multipeaked intermediate-mode solitary pulses is demonstrated.
A jitter model and signal processing techniques are discussed for data recovery in Pulse Width Modulation (PWM) optical recording. In PWM, information is stored through modulating sizes of sequential marks alternating in magnetic polarization or in material structure. Jitter, defined as the deviation from the original mark size in the time domain, will result in error detection if it is excessively large. A new approach is taken in data recovery by first using a high speed counter clock to convert time marks to amplitude marks, and signal processing techniques are used to minimize jitter according to the jitter model. The signal processing techniques include motor speed and intersymbol interference equalization, differential and additive detection, and differential and additive modulation.
Smooth phase interpolated keying (SPIK) is an improved method of computing smooth phase-modulation waveforms for radio communication systems that convey digital information. SPIK is applicable to a variety of phase-shift-keying (PSK) modulation schemes, including quaternary PSK (QPSK), octonary PSK (8PSK), and 16PSK. In comparison with a related prior method, SPIK offers advantages of better performance and less complexity of implementation. In a PSK scheme, the underlying information waveform that one seeks to convey consists of discrete rectangular steps, but the spectral width of such a waveform is excessive for practical radio communication. Therefore, the problem is to smooth the step phase waveform in such a manner as to maintain power and bandwidth efficiency without incurring an unacceptably large error rate and without introducing undesired variations in the amplitude of the affected radio signal. Although the ideal constellation of PSK phasor points does not cause amplitude variations, filtering of the modulation waveform (in which, typically, a rectangular pulse is converted to a square-root raised cosine pulse) causes amplitude fluctuations. If a power-efficient nonlinear amplifier is used in the radio communication system, the fluctuating-amplitude signal can undergo significant spectral regrowth, thus compromising the bandwidth efficiency of the system. In the related prior method, one seeks to solve the problem in a procedure that comprises two major steps: phase-value generation and phase interpolation. SPIK follows the two-step approach of the related prior method, but the details of the steps are different. In the phase-value-generation step, the phase values of symbols in the PSK constellation are determined by a phase function that is said to be maximally smooth and that is chosen to minimize the spectral spread of the modulated signal. In this step, the constellation is divided into two groups by assigning, to information symbols, phase values that result in equal numbers of clockwise and counter-clockwise phase rotations for equally likely symbols. The purpose served by assigning phase values in this way is to prevent unnecessary generation of spectral lines and prevent net shifts of the carrier signal. In the phase-interpolation step, the smooth phase values are interpolated over a number, n, of consecutive symbols (including the present symbol) by means of an unconventional spline curve fit.
A circuit generates sinusoidal excitation signals for a shaft-angle resolver and, like the arctangent circuit described in the preceding article, generates an analog voltage proportional to the shaft angle. The disadvantages of the circuit described in the preceding article arise from the fact that it must be made from precise analog subcircuits, including a functional block capable of implementing some trigonometric identities; this circuitry tends to be expensive, sensitive to noise, and susceptible to errors caused by temperature-induced drifts and imprecise matching of gains and phases. These disadvantages are overcome by the design of the present circuit. The present circuit (see figure) includes an excitation circuit, which generates signals Ksin(Omega(t)) and Kcos(Omega(t)) [where K is an amplitude, Omega denotes 2(pi)x a carrier frequency (the design value of which is 10 kHz), and t denotes time]. These signals are applied to the excitation terminals of a shaft-angle resolver, causing the resolver to put out signals C sin(Omega(t)-Theta) and C cos(Omega(t)-Theta). The cosine excitation signal and the cosine resolver output signal are processed through inverting comparator circuits, which are configured to function as inverting squarers, to obtain logic-level or square-wave signals .-LL[cos(Omega(t)] and -LL[cos(Omega(t)-Theta)], respectively. These signals are fed as inputs to a block containing digital logic circuits that effectively measure the phase difference (which equals Theta between the two logic-level signals). The output of this block is a pulse-width-modulated signal, PWM(Theta), the time-averaged value of which ranges from 0 to 5 VDC as Theta ranges from .180 to +180deg. PWM(Theta) is fed to a block of amplifying and level-shifting circuitry, which converts the input PWM waveform to an output waveform that switches between precise reference voltage levels of +10 and -10 V. This waveform is processed by a two-pole, low-pass filter, which removes the carrier-frequency component. The final output signal is a DC potential, proportional to Theta that ranges continuously from -10 V at Theta = -180deg to +10 V at Theta = +180deg..