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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

A PWM Strategy for Cascaded H-bridges to Reduce the Loss Caused by Parasitic Capacitances of Medium Voltage Dual Active Bridge Transformers

In this paper, to reduce the power loss caused by the parasitic capacitances of medium voltage medium frequency transformers in a two-stage dc/ac converter, including a dual active bridge (DAB)-based dc/dc stage and a cascaded H-bridge (CHB)-based dc/ac stage, a PWM strategy is proposed for the dc/ac stage. For each H-bridge, by shifting the high switching frequency to one half-bridge and having the other half-bridge switching at the fundamental frequency of the ac voltage, equivalent frequencies of transformer terminal-to-ground voltages are reduced. As a result, the frequencies of charging and discharging current to the parasitic capacitance are reduced, and therefore the loss caused by the parasitic capacitances is reduced. Compared to the conventional phase-shift PWM, the proposed PWM strategy can reduce the parasitic capacitance loss by about 75%. Experimental test results of one phase in the 13.8 kV/ 100 kW converter prototype are provided to validate the approach.

Li, Haiguo↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2021

Capacitive wireless power transfer circuit and related techniques

Capacitive wireless power transfer systems are provided. In one embodiment, for example, the system comprises two pair of coupled conducting plates; a first matching network coupled to the first pair of conducting plates; and a second matching network coupled to the second pair of conducting plates. At least one of the first and second matching networks comprises an inductor having inductance value selected based on at least one parasitic capacitance value of the capacitive wireless power transfer system. In another embodiment, a method of designing a capacitive wireless power transfer system is provided comprising determining a parasitic capacitance value of a capacitive wireless power transfer system and determining an inductance value of an inductor of at least one of the first and second matching network having a value selected based on at least one parasitic capacitance value of the capacitive wireless power transfer system.

Afridi, Khurram K.↗
DOE OSTI2022

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC mosfet -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

42 ENGINEERING↗
DOE OSTI2023

A Threshold Helium Leakage Detection Switch with Ultra Low Power Operation

Detecting helium leakage is important in many applications, such as in dry cask nuclear waste storage systems. This work develops a helium detection system based on the relative permittivity (dielectric constant) difference between air and helium. This difference changes the status of an electrostatic microelectromechanical system (MEMS) switch. The switch is a capacitive-based device and requires a very negligible amount of power. Exciting the switch’s electrical resonance enhances the MEMS switch sensitivity to detect low helium concentration. This work simulates two different MEMS switch configurations: a cantilever-based MEMS modeled as a single-degree-freedom model and a clamped-clamped beam MEMS molded using the COMSOL Multiphysics finite-element software. While both configurations demonstrate the switch’s simple operation concept, the clamped-clamped beam was selected for detailed parametric characterization due to its comprehensive modeling approach. The beam detects at least 5% helium concentration levels when excited at 3.8 MHz, near electrical resonance. The switch performance decreases at lower excitation frequencies or increases the circuit resistance. The MEMS sensor detection level was relatively immune to beam thickness and parasitic capacitance changes. However, higher parasitic capacitance increases the switch’s susceptibility to errors, fluctuations, and uncertainties.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
NASA NTRS2016

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

dielectric performance↗
DOE OSTI2020

Loop Antennas for Use On/Off Ground Planes

Many applications benefit from the ability of an RFID tag to operate both on and off a conducting ground plane. This paper presents an electrically small loop antenna at 433 MHz that passively maintains its free-space tune and match when located a certain distance away from a large conducting ground plane. The design achieves this using a single radiation mechanism (that of a loop) in both environments without the use of a ground plane or EBG/AMC structure. An equivalent circuit model is developed that explains the dual-environment behavior and shows that the geometry balances inductive and capacitive parasitics introduced by the ground plane such that the free-space loop reactance, and thus resonant frequency, does not change. A design equation for balancing the inductive and capacitive parasitic effects is derived. Finally, experimental data showing the design eliminates ground plane detuning in practice is presented. The design is suitable for active, “hard” RFID tag applications.

42 ENGINEERING↗
DOE OSTI2020

Investigation of Various Transformer Topologies for HF Isolation Applications

High-frequency (HF) transformers are an essential part of many power electronic devices. The performance and behavior of HF transformers can greatly affect the efficiency and performance of all systems, particularly, from a parasitic parameter point of view. In this article, HF transformers' parasitic parameters, such as leakage inductances and parasitic capacitances, are analyzed using a novel analytical method, finite element method (FEM), and experimental measurements of different structures and winding arrangements. Also, the magnetic field, electric field, electric displacement field, and electric potential distribution within the transformers are simulated and analyzed. Four different HF transformers with E and U cores with different windings are designed and analyzed. Investigation outcomes help to classify structures according to the trade-off between leakage inductances and series parasitic capacitances. This information can later be used for the optimal selection and design of transformers as a function of their operating frequency for any power rating and voltage level. Moreover, 3-D FEM and experimental results validate the proposed methodology to be used for designing HF transformers in high-voltage/power applications.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS2006

Carbon-Nanotube Schottky Diodes

Schottky diodes based on semiconducting single-walled carbon nanotubes are being developed as essential components of the next generation of submillimeter-wave sensors and sources. Initial performance predictions have shown that the performance characteristics of these devices can exceed those of the state-of-the-art solid-state Schottky diodes that have been the components of choice for room-temperature submillimeter-wave sensors for more than 50 years. For state-of-the-art Schottky diodes used as detectors at frequencies above a few hundred gigahertz, the inherent parasitic capacitances associated with their semiconductor junction areas and the resistances associated with low electron mobilities limit achievable sensitivity. The performance of such a detector falls off approximately exponentially with frequency above 500 GHz. Moreover, when used as frequency multipliers for generating signals, state-of-the-art solid-state Schottky diodes exhibit extremely low efficiencies, generally putting out only micro-watts of power at frequencies up to 1.5 THz. The shortcomings of the state-of-the-art solid-state Schottky diodes can be overcome by exploiting the unique electronic properties of semiconducting carbon nanotubes. A single-walled carbon nanotube can be metallic or semiconducting, depending on its chirality, and exhibits high electron mobility (recently reported to be approx.= 2x10(exp 5)sq cm/V-s) and low parasitic capacitance. Because of the narrowness of nanotubes, Schottky diodes based on carbon nanotubes have ultra-small junction areas (of the order of a few square nanometers) and consequent junction capacitances of the order of 10(exp -18) F, which translates to cutoff frequency >5 THz. Because the turn-on power levels of these devices are very low (of the order of nano-watts), the input power levels needed for pumping local oscillators containing these devices should be lower than those needed for local oscillators containing state-of-the-art solid-state Schottky diodes.

Manohara, Harish↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
NASA NTRS2000

Radio Frequency (RF) Micro-Electromechanical Systems (MEMS) Switches for Space Communications

Micro-electromechanical systems (MEMS) is an emerging technology for radio frequency (RF) systems because it has the potential to dramatically decrease loss and improve efficiency. In this paper, we address the design and fabrication of novel MEMS switches being developed at NASA Glenn Research Center. Two types of switches are being developed: a microstrip series single pole single throw (SPST) switch and a coplanar waveguide (CPW) series SPST and single pole double throw (SPDT) switches. These are being fabricated as an integral part of 50 Ohm microstrip and CPW RF integrated circuits using microfabrication techniques. The construction of the switch relies on a cantilever beam that is partially supported by a dielectric post. The cantilever beam is electro-magnetically actuated. To decrease stiction, a Si3N4 thin film is deposited over the contact area. Thus, when the switch is closed, the ON-state insertion loss is governed by the parallel plate capacitance formed by the two contacts. The isolation in the OFF-state is governed by the parasitic capacitance when the cantilever is in the up position. RF MEMS switches have been demonstrated with 80% lower insertion loss than conventional solid state devices (GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and Silicon PIN diodes) based switches. For example, a conventional GaAs five-bit phase shifter which is required for beam steering in a phased array antenna has approximately 7 dB of insertion loss at 26.5 GHz where as a comparable MEMS based phase shifter is expected to have only 2 dB of insertion loss. This translates into 56% lower power dissipation and therefore decreases the thermal load on the spacecraft and also reduces the power amplifier requirements. These benefits will enable NASA to build the next generation of deep space science crafts and micro/nano satellites.

Simons, Rainee N.↗
NASA NTRS1990

Fabrication and optimization of a whiskerless Schottky barrier diode for submillimeter wave applications

The following accomplishments were made towards the goal of an optimized whiskerless diode chip for submillimeter wavelength applications. (1) Surface channel whiskerless diode structure was developed which offers excellent DC and RF characteristics, reduced shunt capacitance and simplified fabrication compared to mesa and proton isolated structures. (2) Reliable fabrication technology was developed for the surface channel structure. The new anode plating technology is a major improvement. (3) DC and RF characterization of the surface channel diode was compared with whisker contacted diodes. This data indicates electrical performance as good as the best reported for similar whisker contacted devices. (4) Additional batches of surface channel diodes were fabricated with excellent I-V and reduced shunt capacitance. (5) Large scale capacitance modelinng was done for the planar diode structure. This work revealed the importance of removing the substrate gallium arsenide for absolute minimum pad capacitance. (6) A surface channel diode was developed on quartz substrate and this substrate was completely removed after diode mounting for minimum parasitic capacitance. This work continues with the goal of producing excellent quality submillimeter wavelength planar diodes which satisfy the requirements of easy handling and robustness. These devices will allow the routine implementation of Schottky receivers into space-based applications at frequencies as high as 1 THz, and, in the future, beyond.

Bishop, W.↗
NASA NTRS2009

Resonance-induced sensitivity enhancement method for conductivity sensors

Methods and systems for improving the sensitivity of a variety of conductivity sensing devices, in particular capacitively-coupled contactless conductivity detectors. A parallel inductor is added to the conductivity sensor. The sensor with the parallel inductor is operated at a resonant frequency of the equivalent circuit model. At the resonant frequency, parasitic capacitances that are either in series or in parallel with the conductance (and possibly a series resistance) is substantially removed from the equivalent circuit, leaving a purely resistive impedance. An appreciably higher sensor sensitivity results. Experimental verification shows that sensitivity improvements of the order of 10,000-fold are possible. Examples of detecting particulates with high precision by application of the apparatus and methods of operation are described.

Tai, Yu-Chong↗
DOE OSTI2024

Modeling the Impacts of Material Properties on Oscillatory Neuron Behavior

In this study, neuromorphic computing, which mimics the functions of biological brains, offers improvements in both latency and energy efficiency over typical von Neumann computing architectures. Spiking neural networks can be especially power-efficient because they encode information temporally and can use more sparse electrical inputs. Here, we study the design of volatile memristors (variable resistors with memory) for neuronal devices, with particular consideration toward the feasibility of all-on-chip oscillation using built-in capacitance. We use circuit simulations to model the behavior of oscillator neurons with a range of realistic material properties. We find that energy inputs increase with insulating-phase resistivity, thermal conductivity, and device aspect ratio. However, we also find that the minimum capacitance needed for oscillation decreases with increasing insulating-phase resistivity, which opposes the constraints for power efficiency. Based on published data on NbO 2 , VO 2 , and EuNiO 3 , we find that existing materials can be engineered for all-on-chip spiking using their parasitic capacitance.

36 MATERIALS SCIENCE↗
NASA NTRS1994

Capaciflector camera

A capacitive type proximity sensor having improved range and sensitivity between a surface and an intruding object in the vicinity of the surface having a voltage source, a number of outer electrical conductors on the surface with each forming one electrode of a number of sensor capacitors, the other electrode for each sensor capacitor being the object. The outer conductors are made from thin sheets of conductive material covered with insulation. An intermediate electrical conductor is located between the outer conductors and the surface and is of a size larger than the outer conductors to act as a shield for reducing the parasitic capacitance between the outer conductors and the surface. The intermediate conductor is also made from a thin sheet of conductive material covered with insulation. The outer conductors and the intermediate conductor are attached to the surface with no gap between the insulation on the conductors and no gap between the surface and the insulation on intermediate conductor, the outer conductors and the intermediate conductor conjoining with each other and with the surface, with the surface acting as a ground plane. A current-measuring voltage follower circuit is connected to the voltage source for coupling in phase and amplitude the instantaneous voltage at the voltage source to the outer electrical conductors and the intermediate electrical conductor. This circuit is responsive to the change in capacitance of the sensor capacitors and generates a number of output signals.

Vranish, John M.↗
NASA NTRS1993

Capaciflector camera

A capacitive type proximity sensor having improved range and sensitivity between a surface and an intruding object in the vicinity of the surface having a voltage source, a number of outer electrical conductors on the surface with each forming one electrode of a number of sensor capacitors, the other electrode for each sensor capacitor being the object is described. The outer conductors are made from thin sheets of conductive material covered with insulation. An intermediate electrical conductor is located between the outer conductors and the surface and is of a size larger than the outer conductors to act as a shield for reducing the parasitic capacitance between the outer conductors and the surface. The intermediate conductor is also made from a thin sheet of conductive material covered with insulation. The outer conductors and the intermediate conductor are attached to the surface with no gap between the insulation on the conductors and no gap between the surface and the insulation on intermediate conductor, the outer conductors and the intermediate conductor conjoining with each other and with the surface, with the surface acting as a ground plane. A current-measuring voltage follower circuit is connected to the voltage source for coupling in phase and amplitude the instantaneous voltage at the voltage source to the outer electrical conductors and the intermediate electrical conductor. This circuit is responsive to the change in capacitance of the sensor capacitors and generates a number of output signals.

Vranish, John M.↗
NASA NTRS1994

Steering capaciflector sensor

A capacitive type proximity sensor having substantial range and sensitivity between a machine and an intruding object in the immediate vicinity of the machine and having a steerable sensing field has an outer electrical conductor on the machine forming one electrode of a sensor capacitor, the other electrode is the object. The outer conductor is a thin sheet of conductive material with a pair (or more) of intermediate electrical conductors located between the outer conductor and the machine. The pair of intermediate electrical conductors are in close proximity to each other and together form a surface having a size substantially larger than the outer conductor to act as a shield for reducing the parasitic capacitance between the outer conductor and the machine and to steer the sensor field. The pair of intermediate conductors are thin sheets of conductive material substantially wider than the first conductor. The outer and pair of intermediate conductors are attached to a surface on the machine in electrical isolation and with no gaps between the conductors and no gap between the surface and the pair of intermediate conductors. The outer and pair of intermediate conductors are also in conformance with each other and the surface of the machine, and the surface of the machine acts as a ground plane. Variable gain voltage follower circuits are used for coupling, in phase, the instantaneous voltage at the outer electrical conductor to the pair of intermediate electrical conductors and a signal generator is coupled to the outer conductor and is responsive to the capacitance of the sensor capacitor for generating a control signal to the machine.

Jenstrom, Del T.↗
NASA NTRS2003

Capacitor-Chain Successive-Approximation ADC

A proposed successive-approximation analog-to-digital converter (ADC) would contain a capacitively terminated chain of identical capacitor cells. Like a conventional successive-approximation ADC containing a bank of binary-scaled capacitors, the proposed ADC would store an input voltage on a sample-and-hold capacitor and would digitize the stored input voltage by finding the closest match between this voltage and a capacitively generated sum of binary fractions of a reference voltage (Vref). However, the proposed capacitor-chain ADC would offer two major advantages over a conventional binary-scaled-capacitor ADC: (1) In a conventional ADC that digitizes to n bits, the largest capacitor (representing the most significant bit) must have 2(exp n-1) times as much capacitance, and hence, approximately 2(exp n-1) times as much area as does the smallest capacitor (representing the least significant bit), so that the total capacitor area must be 2(exp n) times that of the smallest capacitor. In the proposed capacitor-chain ADC, there would be three capacitors per cell, each approximately equal to the smallest capacitor in the conventional ADC, and there would be one cell per bit. Therefore, the total capacitor area would be only about 3(exp n) times that of the smallest capacitor. The net result would be that the proposed ADC could be considerably smaller than the conventional ADC. (2) Because of edge effects, parasitic capacitances, and manufacturing tolerances, it is difficult to make capacitor banks in which the values of capacitance are scaled by powers of 2 to the required precision. In contrast, because all the capacitors in the proposed ADC would be identical, the problem of precise binary scaling would not arise.

Cunningham, Thomas↗