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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Electrical Performance of a High Temperature 32-I/O HTCC Alumina Package

A high temperature co-fired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550 C, and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high temperature packaging applications. This paper introduces a prototype 32-I/O (input/output) HTCC alumina package with platinum conductor for 500 C low-power silicon carbide (SiC) integrated circuits. The design and electrical performance of this package including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550 C are discussed in detail. The parasitic capacitance and parallel conductance of this package in the entire frequency and temperature ranges measured does not exceed 1.5 pF and 0.05 microsiemens, respectively. SiC integrated circuits using this package and compatible printed circuit board have been successfully tested at 500 C for over 3736 hours continuously, and at 700 C for over 140 hours. Some test examples of SiC integrated circuits with this packaging system are presented. This package is the key to prolonged T greater than or equal to 500 C operational testing of the new generation of SiC high temperature integrated circuits and other devices currently under development at NASA Glenn Research Center.

dielectric performance↗
NASA NTRS2006

Carbon-Nanotube Schottky Diodes

Schottky diodes based on semiconducting single-walled carbon nanotubes are being developed as essential components of the next generation of submillimeter-wave sensors and sources. Initial performance predictions have shown that the performance characteristics of these devices can exceed those of the state-of-the-art solid-state Schottky diodes that have been the components of choice for room-temperature submillimeter-wave sensors for more than 50 years. For state-of-the-art Schottky diodes used as detectors at frequencies above a few hundred gigahertz, the inherent parasitic capacitances associated with their semiconductor junction areas and the resistances associated with low electron mobilities limit achievable sensitivity. The performance of such a detector falls off approximately exponentially with frequency above 500 GHz. Moreover, when used as frequency multipliers for generating signals, state-of-the-art solid-state Schottky diodes exhibit extremely low efficiencies, generally putting out only micro-watts of power at frequencies up to 1.5 THz. The shortcomings of the state-of-the-art solid-state Schottky diodes can be overcome by exploiting the unique electronic properties of semiconducting carbon nanotubes. A single-walled carbon nanotube can be metallic or semiconducting, depending on its chirality, and exhibits high electron mobility (recently reported to be approx.= 2x10(exp 5)sq cm/V-s) and low parasitic capacitance. Because of the narrowness of nanotubes, Schottky diodes based on carbon nanotubes have ultra-small junction areas (of the order of a few square nanometers) and consequent junction capacitances of the order of 10(exp -18) F, which translates to cutoff frequency >5 THz. Because the turn-on power levels of these devices are very low (of the order of nano-watts), the input power levels needed for pumping local oscillators containing these devices should be lower than those needed for local oscillators containing state-of-the-art solid-state Schottky diodes.

Manohara, Harish↗
NASA NTRS2000

Radio Frequency (RF) Micro-Electromechanical Systems (MEMS) Switches for Space Communications

Micro-electromechanical systems (MEMS) is an emerging technology for radio frequency (RF) systems because it has the potential to dramatically decrease loss and improve efficiency. In this paper, we address the design and fabrication of novel MEMS switches being developed at NASA Glenn Research Center. Two types of switches are being developed: a microstrip series single pole single throw (SPST) switch and a coplanar waveguide (CPW) series SPST and single pole double throw (SPDT) switches. These are being fabricated as an integral part of 50 Ohm microstrip and CPW RF integrated circuits using microfabrication techniques. The construction of the switch relies on a cantilever beam that is partially supported by a dielectric post. The cantilever beam is electro-magnetically actuated. To decrease stiction, a Si3N4 thin film is deposited over the contact area. Thus, when the switch is closed, the ON-state insertion loss is governed by the parallel plate capacitance formed by the two contacts. The isolation in the OFF-state is governed by the parasitic capacitance when the cantilever is in the up position. RF MEMS switches have been demonstrated with 80% lower insertion loss than conventional solid state devices (GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and Silicon PIN diodes) based switches. For example, a conventional GaAs five-bit phase shifter which is required for beam steering in a phased array antenna has approximately 7 dB of insertion loss at 26.5 GHz where as a comparable MEMS based phase shifter is expected to have only 2 dB of insertion loss. This translates into 56% lower power dissipation and therefore decreases the thermal load on the spacecraft and also reduces the power amplifier requirements. These benefits will enable NASA to build the next generation of deep space science crafts and micro/nano satellites.

Simons, Rainee N.↗
NASA NTRS1990

Fabrication and optimization of a whiskerless Schottky barrier diode for submillimeter wave applications

The following accomplishments were made towards the goal of an optimized whiskerless diode chip for submillimeter wavelength applications. (1) Surface channel whiskerless diode structure was developed which offers excellent DC and RF characteristics, reduced shunt capacitance and simplified fabrication compared to mesa and proton isolated structures. (2) Reliable fabrication technology was developed for the surface channel structure. The new anode plating technology is a major improvement. (3) DC and RF characterization of the surface channel diode was compared with whisker contacted diodes. This data indicates electrical performance as good as the best reported for similar whisker contacted devices. (4) Additional batches of surface channel diodes were fabricated with excellent I-V and reduced shunt capacitance. (5) Large scale capacitance modelinng was done for the planar diode structure. This work revealed the importance of removing the substrate gallium arsenide for absolute minimum pad capacitance. (6) A surface channel diode was developed on quartz substrate and this substrate was completely removed after diode mounting for minimum parasitic capacitance. This work continues with the goal of producing excellent quality submillimeter wavelength planar diodes which satisfy the requirements of easy handling and robustness. These devices will allow the routine implementation of Schottky receivers into space-based applications at frequencies as high as 1 THz, and, in the future, beyond.

Bishop, W.↗
NASA NTRS2009

Resonance-induced sensitivity enhancement method for conductivity sensors

Methods and systems for improving the sensitivity of a variety of conductivity sensing devices, in particular capacitively-coupled contactless conductivity detectors. A parallel inductor is added to the conductivity sensor. The sensor with the parallel inductor is operated at a resonant frequency of the equivalent circuit model. At the resonant frequency, parasitic capacitances that are either in series or in parallel with the conductance (and possibly a series resistance) is substantially removed from the equivalent circuit, leaving a purely resistive impedance. An appreciably higher sensor sensitivity results. Experimental verification shows that sensitivity improvements of the order of 10,000-fold are possible. Examples of detecting particulates with high precision by application of the apparatus and methods of operation are described.

Tai, Yu-Chong↗
NASA NTRS1994

Capaciflector camera

A capacitive type proximity sensor having improved range and sensitivity between a surface and an intruding object in the vicinity of the surface having a voltage source, a number of outer electrical conductors on the surface with each forming one electrode of a number of sensor capacitors, the other electrode for each sensor capacitor being the object. The outer conductors are made from thin sheets of conductive material covered with insulation. An intermediate electrical conductor is located between the outer conductors and the surface and is of a size larger than the outer conductors to act as a shield for reducing the parasitic capacitance between the outer conductors and the surface. The intermediate conductor is also made from a thin sheet of conductive material covered with insulation. The outer conductors and the intermediate conductor are attached to the surface with no gap between the insulation on the conductors and no gap between the surface and the insulation on intermediate conductor, the outer conductors and the intermediate conductor conjoining with each other and with the surface, with the surface acting as a ground plane. A current-measuring voltage follower circuit is connected to the voltage source for coupling in phase and amplitude the instantaneous voltage at the voltage source to the outer electrical conductors and the intermediate electrical conductor. This circuit is responsive to the change in capacitance of the sensor capacitors and generates a number of output signals.

Vranish, John M.↗
NASA NTRS1993

Capaciflector camera

A capacitive type proximity sensor having improved range and sensitivity between a surface and an intruding object in the vicinity of the surface having a voltage source, a number of outer electrical conductors on the surface with each forming one electrode of a number of sensor capacitors, the other electrode for each sensor capacitor being the object is described. The outer conductors are made from thin sheets of conductive material covered with insulation. An intermediate electrical conductor is located between the outer conductors and the surface and is of a size larger than the outer conductors to act as a shield for reducing the parasitic capacitance between the outer conductors and the surface. The intermediate conductor is also made from a thin sheet of conductive material covered with insulation. The outer conductors and the intermediate conductor are attached to the surface with no gap between the insulation on the conductors and no gap between the surface and the insulation on intermediate conductor, the outer conductors and the intermediate conductor conjoining with each other and with the surface, with the surface acting as a ground plane. A current-measuring voltage follower circuit is connected to the voltage source for coupling in phase and amplitude the instantaneous voltage at the voltage source to the outer electrical conductors and the intermediate electrical conductor. This circuit is responsive to the change in capacitance of the sensor capacitors and generates a number of output signals.

Vranish, John M.↗
NASA NTRS1994

Steering capaciflector sensor

A capacitive type proximity sensor having substantial range and sensitivity between a machine and an intruding object in the immediate vicinity of the machine and having a steerable sensing field has an outer electrical conductor on the machine forming one electrode of a sensor capacitor, the other electrode is the object. The outer conductor is a thin sheet of conductive material with a pair (or more) of intermediate electrical conductors located between the outer conductor and the machine. The pair of intermediate electrical conductors are in close proximity to each other and together form a surface having a size substantially larger than the outer conductor to act as a shield for reducing the parasitic capacitance between the outer conductor and the machine and to steer the sensor field. The pair of intermediate conductors are thin sheets of conductive material substantially wider than the first conductor. The outer and pair of intermediate conductors are attached to a surface on the machine in electrical isolation and with no gaps between the conductors and no gap between the surface and the pair of intermediate conductors. The outer and pair of intermediate conductors are also in conformance with each other and the surface of the machine, and the surface of the machine acts as a ground plane. Variable gain voltage follower circuits are used for coupling, in phase, the instantaneous voltage at the outer electrical conductor to the pair of intermediate electrical conductors and a signal generator is coupled to the outer conductor and is responsive to the capacitance of the sensor capacitor for generating a control signal to the machine.

Jenstrom, Del T.↗
NASA NTRS2003

Capacitor-Chain Successive-Approximation ADC

A proposed successive-approximation analog-to-digital converter (ADC) would contain a capacitively terminated chain of identical capacitor cells. Like a conventional successive-approximation ADC containing a bank of binary-scaled capacitors, the proposed ADC would store an input voltage on a sample-and-hold capacitor and would digitize the stored input voltage by finding the closest match between this voltage and a capacitively generated sum of binary fractions of a reference voltage (Vref). However, the proposed capacitor-chain ADC would offer two major advantages over a conventional binary-scaled-capacitor ADC: (1) In a conventional ADC that digitizes to n bits, the largest capacitor (representing the most significant bit) must have 2(exp n-1) times as much capacitance, and hence, approximately 2(exp n-1) times as much area as does the smallest capacitor (representing the least significant bit), so that the total capacitor area must be 2(exp n) times that of the smallest capacitor. In the proposed capacitor-chain ADC, there would be three capacitors per cell, each approximately equal to the smallest capacitor in the conventional ADC, and there would be one cell per bit. Therefore, the total capacitor area would be only about 3(exp n) times that of the smallest capacitor. The net result would be that the proposed ADC could be considerably smaller than the conventional ADC. (2) Because of edge effects, parasitic capacitances, and manufacturing tolerances, it is difficult to make capacitor banks in which the values of capacitance are scaled by powers of 2 to the required precision. In contrast, because all the capacitors in the proposed ADC would be identical, the problem of precise binary scaling would not arise.

Cunningham, Thomas↗
NASA NTRS1976

IGFET/SOI fabrication method

Technique increases switching speeds, shortens channel length, reduces parasitic capacitance and gate overlap, and minimizes gate-to-channel capacitance. The p and n sections may be reversed, allowing fabrication of complementary devices.

Feltner, W. R.↗
NASA NTRS1977

Time delay and integration array (TDI) using charge transfer device technology. Phase 2, volume 1: Technical

The 20x9 TDI array was developed to meet the LANDSAT Thematic Mapper Requirements. This array is based upon a self-aligned, transparent gate, buried channel process. The process features: (1) buried channel, four phase, overlapping gate CCD's for high transfer efficiency without fat zero; (2) self-aligned transistors to minimize clock feedthrough and parasitic capacitance; and (3) transparent tin oxide electrode for high quantum efficiency with front surface irradiation. The requirements placed on the array and the performance achieved are summarized. This data is the result of flat field measurements only, no imaging or dynamic target measurements were made during this program. Measurements were performed with two different test stands. The bench test equipment fabricated for this program operated at the 8 micro sec line time and employed simple sampling of the gated MOSFET output video signal. The second stand employed Correlated Doubled Sampling (CDS) and operated at 79.2 micro sec line time.

Source record↗
NASA NTRS1980

Stress-relieved solder joints

Mechanical stress on solder joints is reduced by procedure for soldering electronic components to circuit boards. Procedure was developed for radio-frequency (RF) strip-line circuits, for which dimensions must be carefully controlled to minimize parasitic capacitance and inductance. Procedure consists of loosening component from its mounting after each lead is soldered relieving induced stresses before next soldering step.

Zemenick, C. J.↗
NASA NTRS1981

Ultra high speed image processing techniques

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.

Anthony, T.↗
NASA NTRS1988

Advances in SIS receiver technology

Significant advances in SIS receiver technology since the last Asilomar meeting include: superconductor materials, integrated inductive tuning elements, and planar mounting structures. The effect of these advances is to push the upper frequency operating limit from about 600 to 1500 GHz, and to enhance the feasibility of focal plane arrays of heterodyne receivers. A fundamental high frequency operating limit of SIS mixers is set by the superconducting energy gap. A practical limitation for high frequency operation of SIS junctions is their parasitic capacitance and resistance. The performance of the mixer will be degraded by the Resistor-Capacitor rolloff. Several designs were reported for inductive elements integrated on the same substrate as the SIS junctions to tune out the bulk junction capacitance. Most millimeter SIS-based heterodyne receivers have used waveguide coupling structures. Technology has advanced to the state where programs that have a high probability of success can be defined to produce arrays of SIS receivers for frequencies as high as 1500 GHz.

Frerking, M. A.↗
NASA NTRS1991

Improved Planar Schottky Diode

Modifications of design and fabrication of surface-channel planar Schottky diode (GSC-13063) reduce parasitic capacitances to theoretical minimum, eliminate buried layer of conductive material between anode contact and semi-insulating substrate, and reduce thickness of diode chip. Changes in epitaxial layer structure and additional fabrication steps reduce conversion loss in millimeter and submillimeter mixers.

Bishop, William↗
NASA NTRS1993

A 250 GHz planar low noise Schottky receiver

A planar quasi-optical Schottky receiver based on the quasi-integrated horn antenna has been developed and tested over the 230-280 GHz bandwidth. The receiver consists of a planar GaAs Schottky diode placed at the feed of a dipole-probe suspended on a thin dielectric membrane in an etched-pyramidal horn cavity. The diode has a 1.21 micron anode diameter and a low parasitic capacitance due to the use of an etched surface channel. The antenna-mixer results in a measured DSB conversion loss and noise temperature at 258 GHz of 7.2 dB +/- 0.5 dB and 1310 K +/- 70 K, respectively, at room temperature. The design is compatible with SIS mixers, and the low cost of fabrication and simplicity makes it ideal for submillimeter-wave imaging arrays requiring a 10-20 percent bandwidth.

Ali-Ahmad, Walid Y.↗
NASA NTRS1993

An 86-106 GHz quasi-integrated low noise Schottky receiver

An integrated planar receiver was developed and tested over the 82-112 GHz bandwidth. The quasi-integrated antenna used in the receiver has a high gain, a high Gaussian coupling efficiency, and a wide bandwidth. The novel mixer design consists of a planar GaAs Schottky diode placed at the feed of a dipole-probe suspended inside an integrated horn antenna. The diode uses an etched surface channel and a planar air bridge for reduced parasitic capacitance. At 92 GHz, the room-temperature antenna-mixer exhibits a double sideband conversion loss and noise temperature of 5.5 +/- 0.5 dB and 770 K +/- 50 K, respectively. The measured DSB conversion loss and noise temperature over a 20 GHz bandwidth (86 GHz-106 GHz) remain less than 6.2 dB +/- 0.5 dB and 1000 K +/- 50 K, respectively. The low cost of fabrication and simplicity of the design makes it ideal for millimeter- and submillimeter-wave receivers.

Ali-Ahmad, Walid Y.↗
NASA NTRS1992

Fully-depleted silicon-on-sapphire and its application to advanced VLSI design

In addition to the widely recognized advantages of full dielectric isolation, e.g., reduced parasitic capacitance, transient radiation hardness, and processing simplicity, fully-depleted silicon-on-sapphire offers reduced floating body effects and improved thermal characteristics when compared to other silicon-on-insulator technologies. The properties of this technology and its potential impact on advanced VLSI circuitry will be discussed.

Offord, Bruce W.↗