Search NASA⌕ Search

SEARCH · Search NASA

Results for “Parasitic capacitance”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

A PWM Strategy for Cascaded H-bridges to Reduce the Loss Caused by Parasitic Capacitances of Medium Voltage Dual Active Bridge Transformers

In this paper, to reduce the power loss caused by the parasitic capacitances of medium voltage medium frequency transformers in a two-stage dc/ac converter, including a dual active bridge (DAB)-based dc/dc stage and a cascaded H-bridge (CHB)-based dc/ac stage, a PWM strategy is proposed for the dc/ac stage. For each H-bridge, by shifting the high switching frequency to one half-bridge and having the other half-bridge switching at the fundamental frequency of the ac voltage, equivalent frequencies of transformer terminal-to-ground voltages are reduced. As a result, the frequencies of charging and discharging current to the parasitic capacitance are reduced, and therefore the loss caused by the parasitic capacitances is reduced. Compared to the conventional phase-shift PWM, the proposed PWM strategy can reduce the parasitic capacitance loss by about 75%. Experimental test results of one phase in the 13.8 kV/ 100 kW converter prototype are provided to validate the approach.

Li, Haiguo↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2021

Capacitive wireless power transfer circuit and related techniques

Capacitive wireless power transfer systems are provided. In one embodiment, for example, the system comprises two pair of coupled conducting plates; a first matching network coupled to the first pair of conducting plates; and a second matching network coupled to the second pair of conducting plates. At least one of the first and second matching networks comprises an inductor having inductance value selected based on at least one parasitic capacitance value of the capacitive wireless power transfer system. In another embodiment, a method of designing a capacitive wireless power transfer system is provided comprising determining a parasitic capacitance value of a capacitive wireless power transfer system and determining an inductance value of an inductor of at least one of the first and second matching network having a value selected based on at least one parasitic capacitance value of the capacitive wireless power transfer system.

Afridi, Khurram K.↗
DOE OSTI2022

Improved Double Pulse Test for Accurate Dynamic Characterization of Medium Voltage SiC Devices

This article presents an improved double pulse test (DPT) for accurate dynamic characterization of the medium voltage (MV) silicon carbide device. The difference between low voltage (LV) and MV DPT setup grounding is first introduced, which results in different measurement considerations. Then, parasitic capacitances in the DPT and their impact on the DPT are discussed considering different grounding points and device connections. Approaches are proposed to minimize the impact of parasitic capacitances on DPT results. In addition, the impact of switching V-I timing alignment on the testing results is discussed, compared to that in the LV DPT; a V-I alignment approach is introduced for the MV DPT. A 10 kV/20 A SiC mosfet -based DPT is taken as an example of the improved DPT, and test results show that it can minimize the impact from parasitic and improve the accuracy of the device switching loss estimation.

42 ENGINEERING↗
DOE OSTI2023

A Threshold Helium Leakage Detection Switch with Ultra Low Power Operation

Detecting helium leakage is important in many applications, such as in dry cask nuclear waste storage systems. This work develops a helium detection system based on the relative permittivity (dielectric constant) difference between air and helium. This difference changes the status of an electrostatic microelectromechanical system (MEMS) switch. The switch is a capacitive-based device and requires a very negligible amount of power. Exciting the switch’s electrical resonance enhances the MEMS switch sensitivity to detect low helium concentration. This work simulates two different MEMS switch configurations: a cantilever-based MEMS modeled as a single-degree-freedom model and a clamped-clamped beam MEMS molded using the COMSOL Multiphysics finite-element software. While both configurations demonstrate the switch’s simple operation concept, the clamped-clamped beam was selected for detailed parametric characterization due to its comprehensive modeling approach. The beam detects at least 5% helium concentration levels when excited at 3.8 MHz, near electrical resonance. The switch performance decreases at lower excitation frequencies or increases the circuit resistance. The MEMS sensor detection level was relatively immune to beam thickness and parasitic capacitance changes. However, higher parasitic capacitance increases the switch’s susceptibility to errors, fluctuations, and uncertainties.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
DOE OSTI2020

Loop Antennas for Use On/Off Ground Planes

Many applications benefit from the ability of an RFID tag to operate both on and off a conducting ground plane. This paper presents an electrically small loop antenna at 433 MHz that passively maintains its free-space tune and match when located a certain distance away from a large conducting ground plane. The design achieves this using a single radiation mechanism (that of a loop) in both environments without the use of a ground plane or EBG/AMC structure. An equivalent circuit model is developed that explains the dual-environment behavior and shows that the geometry balances inductive and capacitive parasitics introduced by the ground plane such that the free-space loop reactance, and thus resonant frequency, does not change. A design equation for balancing the inductive and capacitive parasitic effects is derived. Finally, experimental data showing the design eliminates ground plane detuning in practice is presented. The design is suitable for active, “hard” RFID tag applications.

42 ENGINEERING↗
DOE OSTI2020

Investigation of Various Transformer Topologies for HF Isolation Applications

High-frequency (HF) transformers are an essential part of many power electronic devices. The performance and behavior of HF transformers can greatly affect the efficiency and performance of all systems, particularly, from a parasitic parameter point of view. In this article, HF transformers' parasitic parameters, such as leakage inductances and parasitic capacitances, are analyzed using a novel analytical method, finite element method (FEM), and experimental measurements of different structures and winding arrangements. Also, the magnetic field, electric field, electric displacement field, and electric potential distribution within the transformers are simulated and analyzed. Four different HF transformers with E and U cores with different windings are designed and analyzed. Investigation outcomes help to classify structures according to the trade-off between leakage inductances and series parasitic capacitances. This information can later be used for the optimal selection and design of transformers as a function of their operating frequency for any power rating and voltage level. Moreover, 3-D FEM and experimental results validate the proposed methodology to be used for designing HF transformers in high-voltage/power applications.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2024

Modeling the Impacts of Material Properties on Oscillatory Neuron Behavior

In this study, neuromorphic computing, which mimics the functions of biological brains, offers improvements in both latency and energy efficiency over typical von Neumann computing architectures. Spiking neural networks can be especially power-efficient because they encode information temporally and can use more sparse electrical inputs. Here, we study the design of volatile memristors (variable resistors with memory) for neuronal devices, with particular consideration toward the feasibility of all-on-chip oscillation using built-in capacitance. We use circuit simulations to model the behavior of oscillator neurons with a range of realistic material properties. We find that energy inputs increase with insulating-phase resistivity, thermal conductivity, and device aspect ratio. However, we also find that the minimum capacitance needed for oscillation decreases with increasing insulating-phase resistivity, which opposes the constraints for power efficiency. Based on published data on NbO 2 , VO 2 , and EuNiO 3 , we find that existing materials can be engineered for all-on-chip spiking using their parasitic capacitance.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Factors and Considerations for Modeling Loss of a GaN-based Inverter

The article investigates the impacts of four often-neglected factors on the loss model of a GaN-based full-bridge inverter: parasitic capacitance of the devices, dynamics of junction temperature (Tj) under time-varying power dissipation (Ploss), case temperature estimation, and detailed considerations of the passive components. Procedures to calculate the converter loss considering the above factors are proposed and implemented. A 4.5-kW hard-switching inverter prototype using gallium nitrite (GaN) high-electron-mobility transistors is used to experimentally demonstrate the impact of each factor on the converter loss model. Furthermore, it is found that the accuracy of a converter loss model is mainly affected by the passive components at the light load condition, whereas the thermal and loss models of the active components become the major factors as the output power increases. The results show that after considering the above factors, the converter loss discrepancy between calculation and measurement can be reduced from 30.6 W (28%) to 2.5 W (less than 3%) at heavy load (Po = 4.5 kW), while at the light load condition (Po = 500 W), it is reduced from 3.9 W (28%) to 2.6 W (16%). Furthermore, the difference between simulated and measured case temperature of the GaN devices is within 6 °C.

42 ENGINEERING↗
DOE OSTI2024

A high-volume resonator for L-band DNP-NMR

DNP-NMR and EPR experiments that operate at or greater than L-band (i.e., ν 0 (e – ) = 1–2 GHz) are typically limited to maximum sample volumes of several hundred µL. These experiments rely on well-known resonator designs for DNP/EPR irradiation such as the loop-gap resonator and Alderman-Grant coil, where their maximum volumes limit further application to imaging experiments and high-throughput screening beyond L-band. Herein, we demonstrate a birdcage (BC) resonator design that can accommodate several mL of sample while operating around 1.5 GHz. The sample volume is maximized by using two identical BC resonators in a stacked configuration. Simulations are used to optimize the BC design and the performance is validated experimentally with liquid-state Overhauser-DNP-NMR experiments. This BC design exploits just the parasitic capacitance of conductive rings and features no fixed tuning capacitors. An enhancement of –77 is achieved on a 10 mM 4-Amino-TEMPO in H 2 O sample for a 5 mL sample volume. Finally, the associated sample heating is minimal due to the low-E-fields generated and the large sample mass with +3.4 K when driving 100 W for several seconds.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Single channel PICOSEC Micromegas detector with improved time resolution

This paper presents design guidelines and the experimental verification of a single-channel PICOSEC Micromegas (MM) detector with an improved time resolution. The design encompasses the detector board, vessel, auxiliary mechanical parts, and electrical connectivity for high voltage (HV) and signals, focusing on improving the stability, reducing noise, and ensuring signal integrity to optimize timing performance. A notable feature is the simple and fast reassembly procedure, facilitating quick replacement of the detector internal components that allows for an efficient measurement strategy involving different detector components. The paper also examines the influence of parasitic capacitance and inductance on the output signal integrity. To validate the design, a prototype assembly and three interchangeable detector boards with varying readout pad diameters were manufactured. Detectors were initially tested in the laboratory. Finally, the timing performance of the detectors with different pad sizes was verified using 150 GeV muons. Notably, a record time resolution for a PICOSEC Micromegas detector technology with a CsI photocathode of 12.5 ± 0.8 ps was achieved for a detector with 10 mm diameter readout pad size.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Skipper-CCD Output Sensitivity Improvement with a Common Source Cascode Amplifier

A Skipper-CCD output has been traditionally readout in a source follower configuration, also known as common drain, mainly because in this configuration a good compromise between sensitivity, noise and speed is achieved. In this work a different approach is presented: the output transistor is connected in a common source configuration and an external cascode device is added in series, obtaining a voltage gain higher than unity without increasing significantly the parasitic capacitance due to Miller effect and thus increasing the obtained voltage per electron of charge. The proposed output stage improves the sensitivity 3.4 times when compared with the traditionally used stage while keeping almost the same equivalent noise charge.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Towards Scalable 3D Integration of 2T-nC FeRAM with Hundreds of Layer Stacking

In this article, we study the limits of the number of capacitors and read history dependence in a 2T-nC ferroelectric random-access memory (FeRAM) cell, paving the way for its high-density integration toward hundreds of stacked layers. Through a comprehensive experimental and simulation study on the scaling behavior of the 2T-nC FeRAM architecture, we demonstrate: (i) successful fabrication of 2T-64C cells with robust memory operation and clearly distinguishable ‘0’ and ‘1’ states, even in 64- capacitor configurations; (ii) that the parasitic capacitance of the floating node originates predominantly from the linear component of the ferroelectric capacitor, and its impact on n-scaling—due to degraded sense margin—can be mitigated by floating unselected capacitors with enough TΩ isolation; (iii) that sharing write and read transistors among n capacitors introduces a read history dependence issue due to fluctuating floating node voltage (VFN); and (iv) that a proposed FN discharge scheme can effectively eliminate read-sequence dependence, at the cost of reduced read endurance.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
DOE OSTI2021

Planar Transformer With Asymmetric Integrated Leakage Inductance Using Horizontal Air Gap

This article presents a novel planar-based transformer winding and core structure with controllable leakage inductance generation for integrated magnetics applications. As a result of limitations in integrated magnetics from the literature, a new approach is proposed utilizing semi-interleaved windings and controllable leakage via a leakage flux core leg featuring a horizontal air gap. Here, the proposed transformer design is analyzed via detailed reluctance modeling to determine closed-form equations for the magnetizing and asymmetrically distributed leakage inductances. Next, a genetic-algorithm-based multiobjective design optimization problem is developed, seeking to minimize the core and winding losses of the proposed transformer subject to a set of parametric and geometric constraints in a dc-ac dual-active-bridge topology for microinverter applications. The optimization was extended to include other integrated magnetic structures from the literature, where it is determined that the proposed transformer is superior from the perspectives of efficiency, footprint area, and parasitic capacitance. Based on the results of the optimization analysis, two designs with theoretical transformer California Energy Commission (CEC) efficiency drops (i.e., CEC efficiency reduction specifically due to the transformer loss mechanisms) of 1.19% and 0.83% were fabricated and evaluated for electrical and thermal performance in the proposed 40 V, 400 W microinverter.

42 ENGINEERING↗
DOE OSTI2021

MEMS metal-quartz gyroscope

The present disclosure relates to a gyroscope that makes use of a shuttle having a first plurality of fingers, a stator having a second plurality of fingers, at least one fixed support structure, and a plurality of flexors for supporting the shuttle for vibratory motion relative to the stator. The fingers of the shuttle are able to move in a vibratory motion adjacent the fingers of the stator without contacting the fingers of the stator. Portions of the fingers of at least one of the shuttle and the stator also make use of a grounded metal material layer to reduce parasitic capacitive coupling between the fingers of the shuttle and the fingers of the stator.

Park, Sangtae↗