Results for “Pulsed Phase-locked Loop”

An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

In TDC testing and timing system implementations, it is often necessary to generate signal pulses with finely adjustable time intervals. In delay cell–based schemes, the adjustment resolution is constrained by the propagation delay of the cells—typically 15–20 ps per step—and is sensitive to temperature and supply voltage variations. This document presents a fully digital approach that uses two vernier clocks, generated by two stages of cascaded phase-locked loops (PLLs) with a slight frequency difference, to achieve adjustable timing intervals through accumulated phase differences. The scheme was validated on two families of low-cost FPGA devices, achieving adjustable step sizes of 0.67 ps and 0.97 ps.