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Accelerating Scientific Applications With SambaNova Reconfigurable Dataflow Architecture
Here, our exploratory work finds that the SambaNova Reconfigurable Dataflow Architecture (RDA) along with the SambaFlow software stack provides for an attractive system and solution to accelerate AI for science workloads. We have observed the efficacy of using the system with a diverse set of science applications and reasoned their suitability for performance gains over traditional hardware. As the Data-Scale system provides for a very large memory capacity, the system can be used to train models that typically do not fit in a GPU. The architecture also provides for deeper integration with upcoming supercomputers at the Argonne Leadership Computing Facility (ALCF), a US Department of Energy Office of Science user facility, to help advance science insights.
Self-assembled reconfigurable pump architectures via magnetic colloidal swarms
Self-assembled swarms of interactive active units, which are adaptive and dynamically reconfigurable to accommodate different functionalities, represent a promising platform for the development of next-generation robotics. Here, we utilize the emergent collective behavior of active magnetic colloids confined in quasi-two-dimensional arrays of overlapping wells to demonstrate the self-organization of a colloidal swarm into a dynamic pump architecture capable of controlled transport of passive cargo particles. This dynamic architecture provides a global unidirectional looping flow pattern along the entire length of the system. We show that the flow direction of the dynamic swarm-based pump can be externally controlled by a phase shift of a driving magnetic field energizing the swarm. The experimental observations are supported by computational modeling based on phenomenological coarse-grained particle dynamics coupled to shallow-water Navier-Stokes hydrodynamics. In conclusion, our findings demonstrate how the emergent collective behavior of a swarm can be orchestrated into a desired functionality by exploiting the interplay between activity and confinement potentials.
Fail-Safe Logic Design Strategies Within Modern FPGA Architectures
Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.
Reconfiguring DNA Nanotube Architectures via Selective Regulation of Terminating Structures
Molecular assemblies inside cells often undergo structural reconfiguration in response to stimuli to alter their function. Adaptive reconfiguration of cytoskeletal networks, for example, enables cellular shape change, movement, and cargo transport and plays a key role in driving complex processes such as division and differentiation. The cellular cytoskeleton is a self-assembling polymer network composed of simple filaments, so reconfiguration often occurs through the rearrangement of its component filaments’ connectivities. DNA nanotubes have emerged as promising building blocks for constructing programmable synthetic analogs of cytoskeletal networks. Nucleating seeds can control when and where nanotubes grow and capping structures can bind nanotube ends to stop growth. Such seeding and capping structure, collectively called termini, can organize nanotubes into larger architectures. However, these structures cannot be selectively activated or inactivated in response to specific stimuli to rearrange nanotube architectures, a key property of cytoskeletal networks. Here we demonstrate how selective regulation of the binding affinity of DNA nanotube termini for DNA nanotube monomers or nanotube ends can direct the reconfiguration of nanotube architectures. Using DNA hybridization and strand displacement reactions that specifically activate or inactivate four orthogonal nanotube termini, we demonstrate that nanotube architectures can be reconfigured by selective addition or removal of unique termini. Lastly, we show how terminus activation could be a sensitive detector and amplifier of a DNA sequence signal. These results could enable the development of adaptive and multifunctional materials or diagnostic tools.
Integrated On-Board Charger for Dual Motor Based Electric Vehicle Power Train
This paper presents an integrated on-board charger for dual motor based electric vehicle (EV) power train with silicon carbide semiconductor switch-based traction inverters. The proposed charger architecture reconfigures the traction inverters to be used in the battery charging mode, thereby eliminating several high frequency switches and their accessories. The motor windings are reused as line inductors for the power factor correction (PFC) rectifier stage in the charging mode thereby reducing the requirements of magnetic components. The architectures reduce the cost, weight, and volume of the EV power train. Simulation results are presented to demonstrate the working principle of the proposed architecture.
High-fidelity parallel entangling gates on a neutral-atom quantum computer
The ability to perform entangling quantum operations with low error rates in a scalable fashion is a central element of useful quantum information processing. Neutral-atom arrays have recently emerged as a promising quantum computing platform, featuring coherent control over hundreds of qubits and any-to-any gate connectivity in a flexible, dynamically reconfigurable architecture. The main outstanding challenge has been to reduce errors in entangling operations mediated through Rydberg interactions. Here we report the realization of two-qubit entangling gates with 99.5% fidelity on up to 60 atoms in parallel, surpassing the surface-code threshold for error correction. Our method uses fast, single-pulse gates based on optimal control, atomic dark states to reduce scattering and improvements to Rydberg excitation and atom cooling. We benchmark fidelity using several methods based on repeated gate applications, characterize the physical error sources and outline future improvements. Finally, we generalize our method to design entangling gates involving a higher number of qubits, which we demonstrate by realizing low-error three-qubit gates. By enabling high-fidelity operation in a scalable, highly connected system, these advances lay the groundwork for large-scale implementation of quantum algorithms, error-corrected circuits and digital simulations.
Low power on-chip data transmission for wafer-scale monolithic active pixel sensors
Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.
Reconfigurable Intelligent Surfaces in Action for Nonterrestrial Networks
Next-generation communication technology will be made possible by cooperation between terrestrial networks with nonterrestrial networks (NTNs) composed of high-altitude platform stations (HAPSs) and satellites. Further, as humanity embarks on the long road to establish new habitats on other planets, the cooperation between NTNs and deep-space networks (DSNs) will be necessary. In this regard, we propose the use of reconfigurable intelligent surfaces (RISs) to improve coordination between these networks given that RISs perfectly match the size, weight, and power (SWaP) restrictions of operating in space. Here, a comprehensive framework of RIS-assisted nonterrestrial and interplanetary communications is presented that pinpoints challenges, use cases, and open issues. Furthermore, the performance of RIS-assisted NTNs under environmental effects, such as solar scintillation and satellite drag, is discussed in light of simulation results.
Unconventional compute methods and future challenges for superconducting digital computing
Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.
Performance trade-offs in reconfigurable networks for HPC
Designing efficient interconnects to support high-bandwidth and low-latency communication is critical toward realizing high performance computing (HPC) and data center (DC) systems in the exascale era. At extreme computing scales, providing the requisite bandwidth through overprovisioning becomes impractical. These challenges have motivated studies exploring reconfigurable network architectures that can adapt to traffic patterns at runtime using optical circuit switching. Despite the plethora of proposed architectures, surprisingly little is known about the relative performances and trade-offs among different reconfigurable network designs. We aim to bridge this gap by tackling two key issues in reconfigurable network design. First, we study how cost, power consumption, network performance, and scalability vary based on optical circuit switch (OCS) placement in the physical topology. Specifically, we consider two classes of reconfigurable architectures: one that places OCSs between top-of-rack (ToR) switches—ToR-reconfigurable networks (TRNs)—and one that places OCSs between pods of racks—pod-reconfigurable networks (PRNs). Second, we tackle the effects of reconfiguration frequency on network performance. Our results, based on network simulations driven by real HPC and DC workloads, show that while TRNs are optimized for low fan-out communication patterns, they are less suited for carrying high fan-out workloads. PRNs exhibit better overall trade-off, capable of performing comparably to a fully non-blocking fat tree for low fan-out workloads, and significantly outperform TRNs for high fan-out communication patterns.
CQNN: a CGRA-based QNN Framework
We propose a novel Coarse-Grained Reconfigurable Architecture-based (CGRA) QNN acceleration framework, CQNN. CQNN has a large number of basic components for binary functions. By programming CQNN at runtime according to the target QNN models, these basic components are integrated efficiently to support QNN functions with any data-width and hyper-parameter requirements and CQNN is reconfigured to have the optimal architecture for the target models. The framework includes compiler, architecture design, simulator and RTL generator. Experimental results show CQNNs can complete the inference of AlexNet and VGG-16 within 0.13ms and 2.63ms.
Reconfigurable Electrical Networks within a Conductive Hydrogel Composite
Soft materials that exhibit compliance, programmability, and reconfigurability can have a transformative impact as electronic skin for applications in wearable electronics/soft robotics. There has been significant progress in soft conductive materials; however, achieving electrically controlled and reversible changes in conductivity and circuit connectivity remains challenging. To overcome this limitation, a soft material architecture with reconfigurable conductive networks of silver flakes embedded within a hydrogel matrix is presented. The conductive networks can be reversibly created/disconnected through various stimuli, including current, humidity, or temperature. Such stimuli affect electrical connectivity of the hydrogel by controlling its water content, which can be modulated by evaporation under ambient conditions (passive dehydration), evaporation through electrical Joule heating (active dehydration), or absorption of additional water (rehydration). The resulting change in electrical conductivity is reversible and repeatable, endowing the composite with on-demand reconfigurable conductivity. To highlight this material's unique properties, it is shown that conductive traces can be reconfigured after severe damage and revert to lower conductivity after rehydration. Additionally, a quadruped robot is demonstrated that can respond to stimuli by changing direction following exposure to excess water, thereby achieving reprogrammable locomotion behaviors.
Logical quantum processor based on reconfigurable atom arrays
Suppressing errors is the central challenge for useful quantum computing, requiring quantum error correction (QEC) for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays, our system combines high two-qubit gate fidelities, arbitrary connectivity, as well as fully programmable single-qubit rotations and mid-circuit readout. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks, we realize computationally complex sampling circuits with up to 48 logical qubits entangled with hypercube connectivity with 228 logical two-qubit gates and 48 logical CCZ gates. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.
ECRAM Materials, Devices, Circuits and Architectures: A Perspective
Abstract Non‐von‐Neumann computing using neuromorphic systems based on two‐terminal resistive nonvolatile memory elements has emerged as a promising approach, but its full potential has not been realized due to the lack of materials and devices with the appropriate attributes. Unlike memristors, which require large write currents to drive phase transformations or filament growth, electrochemical random access memory (ECRAM) decouples the “write” and “read” operations using a “gate” electrode to tune the conductance state through charge‐transfer reactions, and every electron transferred through the external circuit in ECRAM corresponds to the migration of ≈1 ion used to store analogue information. Like static dopants in traditional semiconductors, electrochemically inserted ions modulate the conductivity by locally perturbing a host's electronic structure; however, ECRAM does so in a dynamic and reversible manner. The resulting change in conductance can span orders of magnitude, from gradual increments needed for analog elements, to large, abrupt changes for dynamically reconfigurable adaptive architectures. In this in‐depth perspective, the history of ECRAM, the recent progress in devices spanning organic, inorganic, and 2D materials, circuits, architectures, the rich portfolio of challenging, fundamental questions, and how ECRAM can be harnessed to realize a new paradigm for low‐power neuromorphic computing are discussed.
Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes
Not Available
Programmable simulations of molecules and materials with reconfigurable quantum processors
Simulations of quantum chemistry and quantum materials are believed to be among the most important applications of quantum information processors. However, realizing practical quantum advantage for such problems is challenging because of the prohibitive computational cost of programming typical problems into quantum hardware. Here we introduce a simulation framework for strongly correlated quantum systems represented by model spin Hamiltonians that uses reconfigurable qubit architectures to simulate real-time dynamics in a programmable way. Our approach also introduces an algorithm for extracting chemically relevant spectral properties via classical co-processing of quantum measurement results. We develop a digital–analogue simulation toolbox for efficient Hamiltonian time evolution using digital Floquet engineering and hardware-optimized multi-qubit operations to accurately realize complex spin–spin interactions. As an example, we propose an implementation based on Rydberg atom arrays. In addition, we show how detailed spectral information can be extracted from the dynamics through snapshot measurements and single-ancilla control, enabling the evaluation of excitation energies and finite-temperature susceptibilities from a single dataset. To illustrate the approach, we show how to use the method to compute key properties of a polynuclear transition-metal catalyst and two-dimensional magnetic materials.
Flexspander: augmenting expander networks in high-performance systems with optical bandwidth steering
Communication efficiency is one of the deciding factors in determining many of today’s high-performance computing (HPC) applications. Traditionally, HPC systems have been on static network topologies, making them inflexible to the variety of skewed traffic demands that may arise due to the spatial locality inherent in many applications. To handle traffic locality, researchers have proposed integrating optical circuit switches (OCSs) into the network architecture, which reconfigures the network topology to alter and dynamically adapt to the predicted traffic. In this paper, we present a novel reconfigurable network topology called Flexspander. Beyond offering a flexible interconnect, Flexspander also offers full flexibility in terms of construction and can be built with any arbitrary combination of commercial electrical packet switches and OCSs. We evaluate Flexspander performance through extensive simulations with multiple network traces, and our results show improved performance for Flexspander over currently proposed static and reconfigurable topologies in terms of the flow completion time.