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Results for “SOI CMOS”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2023

A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm 2 Area Efficiency

Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal cancellation in full-duplex, and for isolation from reflections in signal repeaters. However, programmable broadband RF delay has been limited to ones of ns due to challenges in miniaturization with low loss and low power consumption. In this work, we present a 0.2–2 GHz digitally programmable RF delay element based on a time-interleaved multistage switched-capacitor (TIMS-SC) approach. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. Further, the delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55–448.6 ns programmable delay range with < 0.12% delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm 2 area efficiency. Through the proposed approach, the device shows minimal delay change across a -40 °C to 85 °C temperature range and < 0.25 dB gain variation across delay settings. The device achieves 26 dB gain, 7.4 dB noise figure, and consumes 74 mW from a 1 V supply with an active area of 1.36 mm 2 .

42 ENGINEERING↗
DOE OSTI2018

Fabrication and DC/AC Characterization of 3-Terminal Ferromagnet/Silicon Spintronics Devices

CMOS and SOI technology compatible structures and devices are currently intensively investigated by many research groups, since various effects observed in such structures can be relatively easy implemented in electronic devices thereby expanding their functionality. The most promising is the research and development of spintronic devices, which will allow using both electron charge and spin degrees of freedom for transmission, storage and processing of information. In this work we report the fabrication process of 3-terminal (3-T) ferromagnet/silicon devices of two types. First is the planar Fe{sub 3}Si/Si 3-T structure with 5 μm gap between closest ferromagnetic electrodes. Second is silicon nanowire back-gate transistor with Fe film source and drain synthesized on SOI substrate. Transport and magnetotransport properties of both devices are investigated.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Final Technical Report

Explore the source record for details and available documents.

Gamma detector, avalanche photodiode, nanotechnolo↗
DOE OSTI2012

Final Report

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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Development of a CMOS Oscillator Chain for Particle Detection based on SOI technology

A new development of an oscillator concept, dedicated to the detection and tracking of particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. The very first solution was proposed using bulk technology. This new development is based on SOI technology what makes it tolerant to radiations. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Enhanced spectroscopic gas sensors using in-situ grown carbon nanotubes

In this letter, we present a fully complementary-metal-oxide-semiconductor (CMOS) compatible microelectromechanical system thermopile infrared (IR) detector employing vertically aligned multi-walled carbon nanotubes (CNT) as an advanced nano-engineered radiation absorbing material. The detector was fabricated using a commercial silicon-on-insulator (SOI) process with tungsten metallization, comprising a silicon thermopile and a tungsten resistive micro-heater, both embedded within a dielectric membrane formed by a deep-reactive ion etch following CMOS processing. In-situ CNT growth on the device was achieved by direct thermal chemical vapour deposition using the integrated micro-heater as a micro-reactor. The growth of the CNT absorption layer was verified through scanning electron microscopy, transmission electron microscopy, and Raman spectroscopy. The functional effects of the nanostructured ad-layer were assessed by comparing CNT-coated thermopiles to uncoated thermopiles. Fourier transform IR spectroscopy showed that the radiation absorbing properties of the CNT adlayer significantly enhanced the absorptivity, compared with the uncoated thermopile, across the IR spectrum (3 μm–15.5 μm). This led to a four-fold amplification of the detected infrared signal (4.26 μm) in a CO{sub 2} non-dispersive-IR gas sensor system. The presence of the CNT layer was shown not to degrade the robustness of the uncoated devices, whilst the 50% modulation depth of the detector was only marginally reduced by 1.5 Hz. Moreover, we find that the 50% normalized absorption angular profile is subsequently more collimated by 8°. Our results demonstrate the viability of a CNT-based SOI CMOS IR sensor for low cost air quality monitoring.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

High Linearity RF Circuits in CMOS Platforms (CRADA Final Report)

The goal of this CRADA was to understand high linearity silicon-on-insulator (SOI) radio frequency switches. The first direction investigated was high linearity RF mixers as these components are composed of a network of switches. During the course of the investigation, it was determined that while the SOI RF switches were effective in the application in mixers and produced state of the art performance, the use of SOI for mixers is not economically feasible because the technology only worked with advanced CMOS nodes <65nm which can have an NRE cost (from lithography masks) in excess of $\$$500,000.

42 ENGINEERING↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2016

Methods of producing strain in a semiconductor waveguide and related devices

Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Slow-Light Mid-IR Silicon Photonic Chips for NO 2 and CH 4 Gas Detection

A compact, chip-scale mid-infrared gas sensor is demonstrated, leveraging a two-dimensional photonic crystal waveguide (PCW) fabricated on a silicon-on-insulator (SOI) platform. The PCW comprises a hexagonal lattice with lattice constant a = 860 nm and hole radius r = 0.22a, incorporating a central line defect of reduced-radius holes (r s = 0.7r) to induce slow-light propagation near the photonic band edge with a group index of approximately 73, thereby enhancing light-matter interaction. The sensor operates at fundamental absorption wavelengths of 3.42 μm for nitrogen dioxide (NO 2 ) and 3.40 μm for methane (CH 4 ), utilizing the strongest molecular vibrational transitions for maximum sensitivity. Experimental validation was conducted using dynamically diluted gas mixtures generated by mass flow controllers, with signal acquisition performed by a liquid nitrogen-cooled InSb detector. For NO 2 , the sensor exhibited excellent linear response over 5–25 ppm (part per million) with coefficient of determination R 2 = 0.9934, achieving a detection limit of 210 ppb (part per billion)─representing the first reported silicon photonic-based NO 2 detection. For CH 4 , exposure to 25 ppm resulted in a 6.4% decrease in transmitted intensity, demonstrating multigas sensing capability. The CMOS-compatible fabrication process and compact 3 mm device footprint establish this SOI-PCW platform as a scalable, low-power solution for integrated mid-infrared gas sensing, with significant potential for environmental monitoring and industrial safety applications.

Crystals↗
DOE OSTI2014

III-V/Si on silicon-on-insulator platform for hybrid nanoelectronics

The unique properties of SOI wafers enable the integration of heterogeneous materials with distinct functionalities in different layers. In particular, III-V compound semiconductors are very attractive for low-noise and high-speed electronic and photonic components integrated on a single chip. We have developed a CMOS compatible and fully integrated solution for the integration of III-V compound semiconductors with silicon technology for optoelectronic applications. InAs compound semiconductor nanostructures are synthesized in SOI wafers using the combined ion beam implantation and millisecond liquid-phase epitaxial growth. Optoelectronic and microstructural investigations carried out on implanted, annealed, and selectively etched samples confirm the formation of high-quality III-V compound semiconductor nanostructures.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗