Sensitivity Analysis of a Technique for the Extraction of Interface Trap Density in SiC MOSFETs from Subthreshold Characteristics.
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With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.
The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. Here, a double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.
In a converter based on 10 kV SiC MOSFETs, major sources of parasitic capacitance are the anti-parallel junction barrier schottky (JBS) diode, heat sink, and load inductor. A half bridge phase leg test setup is built to investigate these parasitic capacitors’ impact on the switching performance at 6.25 kV. Generally these parasitic capacitors slows down both turn-on and turn-off transient and can cause significant increase in switching energy loss. The impact of the parasitic capacitor in the load inductor is analyzed, which has either very short wire or long wire in series. Switching performance of the phase leg with two different thermal designs are compared to investigate the impact of the parasitic capacitor due to the heat sink. The large parasitic capacitor due to the large drain plate of discrete 10 kV SiC MOSFET for heat dissipation can result in 44.5% increase in switching energy loss at low load current.
This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. Furthermore, the prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in 3 .
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A modular and scalable SiC MOSFET based universal power electronics regulator (UPER) allows coordinated integration of energy resources and loads, elimination of extra power conversion stages, and allowance of more sources or loads added with a simple plug and play feature. A comprehensive investigation has been conducted in term of the typical distributed generations and loads employed in buildings, in order to outline a detailed specification for UPER. Thus, a common DC bus voltage of 500 V and power rating of 3 kW are dedicatedly selected. The UPER hardware design and implementation are completely illustrated, including the static and dynamic characterization of the employed SiC MOSFET. The dedicated universal power cell and Plug-and-Play gate driver performs reliable continuous operation even exposed to an extreme fast switching speed (> 100 V/ns). The continuous operation of buck mode verified the UPER hardware development at 50 kHz with an overall efficiency of 98.19%. A new voltage polarity reversal phenomenon was also discovered in the verification of the isolated DAB stage with planar transformers.
Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.
Power loss estimation of power electronic devices is important to the efficiency optimization of motor drives used in many applications. However, most existing simplified power loss models of silicon carbide (SiC) MOSFETs are not sufficiently accurate due to their neglect of parasitic parameters in the current commutation loop. In addition, the loss model of the voltage source inverter (VSI) cannot be directly applied to the current source inverter (CSI) because of differences between their commutation loops. First, the commutation processes for VSIs and CSIs are compared. The voltage and current trajectories of SiC MOSFETs in the switching transition of a CSI-based motor drive system are analyzed in detail. Based on these results, the conduction and switching losses of SiC MOSFETs in CSIs are modeled considering the current commutation details. In addition, the proposed analytical model includes parasitic inductances and capacitances in the current commutation loop. Experimental results have verified that the proposed power loss model delivers higher accuracy loss predictions than the conventional loss model.
This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. Here, a thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.
Abstract—This paper presents the hardware design of a 7 kV dc bus,1 MVA, 0-1,000 Hz, 1.7 kV SiC MOSFET based medium voltage variable speed drive (MVVSD)1. The system is based on a 7-level three-phase modular multilevel converter (MMC). The full in-depth design, development, and testing of this prototype are provided, including MMC submodule development, arm inductor design, control hardware realization, system integration and thermal analysis. Finally, experimental results demonstrate the excellent performance of the 1.7 kV SiC MOSFET based submodule and the 1 MW, 7 kV MVVSD as a unity in various operation modes
In this paper, the static and dynamic characteristics of discrete 650 V and 1200 V trench TO 247 SiC MOSFET is evaluated and compared with a similar current rating 1200 V planar gate discrete TO 247 SiC MOSFET. The new trench MOSFET has promising application for vehicle charging and auxiliary power supply application due to the lower on-state resistance and lower capacitance. Static characteristics for these devices are evaluated using a curve tracer for different device junction temperature A common double pulse test (DPT) platform is developed to evaluate the switching loss at different device junction temperature ranging from 25°C to 175°C. The experimental setup and results are presented for different load currents and temperature.
As two exemplary candidates of wide‐bandgap devices, SiC MOSFETs and GaN HEMTs are regarded as successors of Si devices in medium‐to‐high‐voltage (>1200 V) and low‐voltage (<650 V) domains, respectively, thanks to their excellent switching performance and thermal capability. With the introduction of 650 V SiC MOSFETs and GaN HEMTs, the two technologies are in direct competition in <650 V domains, such as Level 2 battery chargers for electric vehicles (EVs). This study applies 650 V SiC and GaN to two 240 VAC/7.2 kW EV battery chargers, respectively, aiming to provide a head‐to‐head comparison of these two devices in terms of overall efficiency, power density, thermal performance, and cost. The charger essentially is an indirect matrix converter with a dual‐active‐bridge stage handling the power factor correction and power delivery simultaneously. These two chargers utilise the same control strategy, varying the phase‐shift and switching frequency to cover the wide input range (80–260 VAC) and wide output range (200 V–450 VDC). Experimental results indicated that at the same efficiency level, the GaN charger is smaller, more efficient and cheaper, while the SiC charger has a better thermal performance.