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Nonuniformly quantized multibit oversampled Sigma-Delta A/D convertors are proposed which achieve high SNR over a wide dynamic range. Simulation results are presented for first- and second-order 4 bit Sigma-Delta A/D convertors with companding internal quantizers.
The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.
A new architecture is presented for a multibit oversampled Sigma-Delta A/D convertor. A novel feedback arrangement is employed to reduce the sensitivity of the overall resolution to the nonlinearity of the multibit DAC. Simulations confirm the improved performance achieved by the proposed structure.
Improved isolation amplifier transmits dc or low-frequency analog signal by use of digital pulses. Relatively imprecise digital pulses convey analog signal with relatively high precision. Amplifier implements sigma-delta modulation scheme. Circuit used wherever conventional amplifier needed. Includes medical instrumentation, switching-type power supplies, and other applications in which input voltages must be measured in presence of large common-mode voltages.
Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.
The sub-orbital rocket mission was a collaborative project between the University of New Hampshire, Cornell University, and the Jet Propulsion Laboratory (JPL) to study filamentation phenomena in the northern Auroral zone. The Enstrophy mission test flies the JPL Free-Flying Magnetometer (FFM) concept. The FFM technology development task has been funded by NASA develop miniaturized, low-power, integrated "sensorcrafts". JPL's role was to design, integrate, test, and deliver four FFMs for deployment from the sounding rocket, allowing a unique determination of curl-B. This provides a direct measurement of magnetic-field-aligned current density along the rocket trajectory. A miniaturized three-axis fluxgate magnetometer was integrated with a 4-channel 22-bit sigma-delta Analog to Digital Converter (ADC), four temperature sensors, digital control electronics, seven (Li-SOCl2) batteries, two (4 deg x 170 deg field of view) sun-sensors, a fan-shaped-beam laser diode beacon, a (16 MHz) stable Temperature Compensated Crystal Oscillator (TCXO) clock, Radio Frequency (RF) communication subsystem, and an antenna for approximately 15 minutes of operation where data was collected continuously and transmitted in three (3) bursts (approximately 26 seconds each) to ground station antennas at Poker Flat, Alaska. FFMs were stowed within two trays onboard the rocket during the rocket launch and were released simultaneously using the spinning action of the rocket at approximately 300 km altitude (approximately 100 sec. into the flight). FFMs were deployed with spin rate of approximately 17 Hz and approximately 3 m/sec linear velocity with respect to the rocket. For testing purposes while the rocket was in the launch pad and during flight prior to release of FFMs from the rocket, commands (such as "power on", "test", "flight", "power off', and clock "Reset" signal) were transmitted via a infrared Light Emitting Diode to an infrared detector in the FFM. Special attention was paid to low magnetic signature electronic design and choice of materials in packaging. The miniaturized fluxgate magnetometers had a range of 1-60000 nT with 0.1% full-scale linearity. The frequency range of interest for magnetic measurement was 10 mHz - 50 Hz. Digital data from the magnetometer's three axes were placed in a 4MB Static Random Access Memory (SRAM) in data packages (frames) formatted together with time tags and frame ID. After a specified time was elapsed, the data were Viterbi encoded and transmitted at a rate of 100 kbps (BPSK). Each of the four FFMs transmitted at different frequency. These carrier frequencies were in the range of 2200-2300 MHz. The antenna was a single patch on a high dielectric constant substrate covering one end-plate of the hockey-puck-sized unit. The local clocks aboard the FFMs were reset at the start of the mission and stayed synchronized within 3 msec during the mission. Position of each FFM with respect to the rocket is calculated by the knowledge of its release velocity (measured at exit point of the FFM launcher tract) providing an accuracy of 1 m over the maximum range of 3 km. Spatial and temporal nature of observants can be separated to within 3 m in space or 3 msec time interval.
A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.
Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.
Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 ??itch in a 1.2 ??-well CMOS process and a 40 ??itch in a 2 ??-well CMOS process. The successive approximation designs consume as little as 49 ??t a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental sigma-delta ADC test chips designed to be multiplied among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 ??t a 5 KHz.
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