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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications

This paper presents the open-source High-Level Synthesis research framework Bambu. The framework provides an open-source starting point to experiment with new ideas across High-Level Synthesis, high-level verification and debugging, FPGA/ASIC design, design flow space exploration, and parallel hardware accelerator design. The tool accepts as input standard C/C++ specifications and compiler intermediate representations (IRs) coming from the well-known Clang/LLVM and GCC com- pilers. The broad spectrum and flexibility of input formats allow the electronic design automation (EDA) research community to explore and integrate new transformations and optimizations. The easily extendable modular framework already includes many op- timizations and HLS benchmarks. The integration with synthesis and verification backends (commercial and open-source) allows researchers to quickly test any new finding and easily obtain performance and resource usage metrics for a given application. Different FPGA devices are supported from several different vendors: AMD/XILINX, Intel/Altera, Lattice Semiconductor, and NanoXplore. Finally, integration with the OpenRoad open-source end-to-end silicon compiler perfectly fits with the recent push towards open-source EDA.

Ferrandi, Fabrizio↗
DOE OSTI2022

SODA Synthesizer: an Open-source, Multi-level, Modular, Extensible Compiler from High-level Frameworks to Silicon

The SODA Synthesizer is an open-source modular, end-to-end hardware compiler framework. The SODA frontend, developed in MLIR, performs system-level design, code partitioning, and high-level optimizations to prepare the specifications for the hardware synthesis. The backend is based on a state-of-the-art high-level synthesis tool, and generates the final hardware design. The backend can interface with logic synthesis tools for field programmable gate arrays or with commercial and open-source logic synthesis tools for application-specific integrated circuits. We discuss the opportunities and challenges in integrating with commercial and open-source tools both at the frontend and backend, and the unique opportunities that an open-source hardware design ecosystem provides.

Bohm Agostini, Nicolas↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Advanced silicone materials for soft actuator applications

Soft actuators are at the forefront of the innovation tide in medicine, manufacturing, and aerospace because they are able to mimic the behavior of biological tissue and adapt to complex, unstructured environments. Of all the materials used, silicone-based elastomers have drawn enormous attention since they offer a superb combination of mechanical flexibility, biocompatibility, thermal stability, and long-term durability. In the past few years, there has also been a rapid pace of material evolution, additive manufacturing, and biointegration that has enhanced the performance and applications of silicone-based soft actuators. However, there is no focused and timely review compiling these advances. This review seeks to address that need by critically discussing recent advancements in advanced silicone materials, exploring new fabrication methodologies, and discussing emerging applications that range from wearable devices to implantable robotics. We also present suggestions for directions and the problems which must be addressed in order to further develop the performance and potential of silicone-based soft actuators, justifying the relevance and urgency of this effort.

biocompatibility↗
DOE OSTI2024

The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗
DOE OSTI2022

Neutron elastic and inelastic cross section measurements on silicon from 0.8--8 MeV

Neutron elastic and inelastic scattering differential cross sections were measured at angles between 30° and 155° with incident neutron energies between 0.8 and 8 MeV. The measured differential scattering cross sections are compared to existing measurements and the ENDF/B-VIII.0, the JEFF-3.3, and the JENDL-4.0 data evaluations, as well as theoretical calculations from the TALYS-1.95 nuclear reaction code. Our results are reasonably well described by values from the ENDF/B-VIII.0 and JEFF-3.3 compilations. However, below 4 MeV, our backward-angle elastic scattering results tend to be lower than database/calculated values, suggesting that less recoil damage would occur than expected. Above 6 MeV, larger backward-angle cross sections are observed suggesting the opposite. Deexcitation γ rays produced in the inelastic scattering process were also studied for neutron energies between 1.9 and 4.5 MeV. Inelastic neutron scattering cross sections deduced from 28 Si(n,n1γ) γ-ray projection cross sections confirm our 28 Si(n,n1) results. To the extent that data from GELINA and our experimental results can be compared, we have excellent agreement between the inelastic neutron scattering cross sections.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

Test and extraction methods for the QC parameters of silicon strip sensors for ATLAS upgrade tracker

The Quality Control (QC) of pre-production strip sensors for the Inner Tracker (ITk) of the ATLAS Inner Detector upgrade has finished, and the collaboration has embarked on the QC test programme for production sensors. This programme will last more than 3 years and comprises the evaluation of approximately 22000 sensors. 8 Types of sensors, 2 barrel and 6 endcap, will be measured at many different collaborating institutes. The sustained throughput requirement of the combined QC processes is around 500 sensors per month in total. Measurement protocols have been established and acceptance criteria have been defined in accordance with the terms agreed with the supplier. For effective monitoring of test results, common data file formats have been agreed upon across the collaboration. To enable evaluation of test results produced by many different test setups at the various collaboration institutes, common algorithms have been developed to collate, evaluate, plot and upload measurement data. This allows for objective application of pass/fail criteria and compilation of corresponding yield data. These scripts have been used to process the data of more than 3000 sensors so far, and have been instrumental for identification of faulty sensors and monitoring of QC testing progress.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis

Domain-specific designs offer greater energy efficiency and performance gain than general-purpose processors. For this reason, modern system-on-chips have a significant portion of their silicon area with custom accelerators. However, designing hardware by hand is laborious and time-consuming, given the large design space and the performance, power, and area constraints that are not realized in the software. Moreover, domain-specific algorithms (e.g., machine learning models) are evolving quickly, challenging the accelerator design further. To address these issues, this paper presents SODA Synthesizer, an automated open-source high-level ML framework to Verilog modular compiler targeting AI/ML Application-Specific Integrated Circuits (ASICs) accelerators. SODA tightly couples the Multi- Level Intermediate Representation (MLIR) compiler infrastructure [24] and open-source HLS approaches. Thus, SODA can support various ML frameworks and algorithms and can perform optimizations that combine specialized architecture templates and conventional HLS to generate the hardware modules. In addition, SODA’s closed-loop design space exploration (DSE) engine allows developers to perform end-to-end design space explorations on different metrics and technology nodes.

Zhang, Jeff↗
DOE OSTI2024

Solar Photovoltaic and Storage Supply Chains and Technology and Market Opportunities

This talk will highlight the most recent efforts from the National Renewable Energy Laboratory (NREL) to track solar photovoltaic (PV) and storage supply and demand in the United States and globally, as well as bottom-up calculations of manufacturing costs for facilities across the globe. We will begin with an overview of the global solar PV supply chain and 2022 benchmark input data used for NREL's bottom-up crystalline silicon (c-Si) and thin film PV module manufacturing cost models. For the polysilicon, wafer, cell conversion, and module assembly steps of the c-Si supply chain, and for thin film modules, we will review the industry-collected input data and methods used for calculating the costs of goods sold (COGS); research and development (R&D) expenses; and sales, general, and business administration (S, G, and A) expenses. This 2022 benchmark analysis is compiled for state-of-the-art c-Si and thin film PV module manufacturing in several countries and regions; and will also include a quantified summary of the impacts of the manufacturing incentives and tax credits that are available for solar manufacturing and installations within the United States. Next generation technologies that lower PV manufacturing and installation costs, reduce operations and maintenance (O&M) expenses, and improve system energy yield will also be highlighted. We will conclude with projections of solar market penetration to 2050 from NREL's Solar Futures Study and Annual Technology Baseline (ATB) model, which includes solar coupled with lower-cost storage scenarios as well as the range of future cost scenarios for other power generation sources. We look forward to sharing NREL's extensive work in these areas and discussing ideas for future directions.

economics↗
DOE OSTI2026

Characterizing Defect Dynamics in Silicon Carbide Using Symmetry-Adapted Collective Variables and Machine Learning Interatomic Potentials

Silicon carbide (SiC) divacancies are attractive candidates for spin-defect qubits possessing long coherence times and optical addressability. The high activation barriers associated with SiC defect formation and motion pose challenges for their study by first-principles molecular dynamics. In this work, we develop and deploy machine learning interatomic potentials (MLIPs) to accelerate defect dynamics simulations while retaining ab initio accuracy. We employ an active learning strategy comprising symmetry-adapted collective variable discovery and enhanced sampling to compile configurationally diverse training data, calculation of energies and forces using density functional theory (DFT), and training of an E(3)-equivariant MLIP based on the Allegro model. Here, the trained MLIP reproduces DFT-level accuracy in defect transition activation free energy barriers, enables the efficient and stable simulation of multidefect 216-atom supercells, and permits an analysis of the temperature dependence of defect thermodynamic stability and formation/annihilation kinetics to propose an optimal annealing temperature to maximally stabilize VV divacancies.

Computer simulations↗
DOE OSTI2022

Solar and Storage Techno-Economic Analysis Tutorial for the IEEE Photovoltaic Specialist Conference (PVSC)

This tutorial will highlight the most recent efforts from the National Renewable Energy Laboratory (NREL) to track solar photovoltaic (PV) technology trends and manufacturing costs, project levelized cost of electricity (LCOE), and project levelized cost of solar plus storage (LCOSS) for systems across the globe. We will begin with an overview of the global PV supply chain and 2021 benchmark input data for NREL's crystalline silicon (c-Si) and thin film PV module manufacturing cost models. The framework that we follow and will review during this tutorial provides a methodology to prepare bottom-up manufacturing cost models including the items within the U.S. Generally Accepted Accounting Principles (GAAP) and the International Financial Reporting Standards (IFRS). For the polysilicon, wafer, cell conversion, and module assembly steps of the c-Si supply chain, and for thin film modules, we will review input data and methods useful for calculating the costs of goods sold (COGS); research and development (R&D) expenses; and sales, general, and business administration (S, G, &A) expenses. This 2021 benchmark analysis is compiled for state-of-the-art c-Si and thin film module manufacturing. We will also review methods for our 2021 system benchmark costs calculations and LCOE technoeconomic analysis of PV systems and solar plus storage systems. Next generation technologies that lower PV manufacturing and installation costs, reduce operations and maintenance (O&M) expenses, and improve system energy yield will also be highlighted. Techniques for comparing LCOE performance will also be reviewed. We look forward to sharing NREL's extensive work in these areas and discussing ideas for future directions.

cost models↗