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At least 19 records

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DOE OSTI2022

Tolerating memory stack failures in multi-stack systems

Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

Mappouras, Georgios↗

DOE OSTI2019

MAC: Memory Access Coalescer for 3D-Stacked Memory

Emerging data-intensive applications, such as graph analytics and data mining, exhibit irregular memory access patterns. Research has shown that with these memory-bound applications, traditional cache-based processor architectures, which exploit locality and regular patterns to mitigate the memory-wall issue, are inefficient. Meantime, novel 3D-stacked memory devices, such as Hybrid Mem- ory Cube (HMC) and High Bandwidth Memory (HBM), promise significant increases in bandwidth that appear extremely appealing for memory-bound applications. However, conventional memory interfaces designed for cache-based architectures and JEDEC DDR devices fit poorly with the 3D-stacked memory, which leads to significant under-utilization of the promised high bandwidth. As a response to these issues, in this paper we propose MAC (Memory Access Coalescer), a coalescing unit for the 3D-stacked memory. We discuss the design and implementation of MAC, in the context of a custom designed cache-less architecture targeted at data-intensive, irregular applications. Through a custom simulation infrastructure based on the RISC-V toolchain, we show that MAC achieves a coalescing efficiency of 52.85% on average. It improves the performance of the memory system by 60.73% on average for a large set of irregular workloads.

Wang, Xi↗

DOE OSTI2021

HAM: Hotspot-Aware Manager for Improving Communications with 3D-Stacked Memory

merging High-Performance Computing (HPC) workloads, such as graph analytics, machine learning, and big data science, are data-intensive. Data-intensive workloads usually present fine-grained memory accesses with limited or no data locality, and thus incur frequent cache misses and low utilization of memory bandwidth. 3D-stacked memory devices such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) can provide significantly higher bandwidth than conventional memory modules. However, the traditional interfaces and optimization methods for JEDEC DDR devices do not allow to fully exploit the potential performance of 3D-stacked memory with the massive amount of irregular memory accesses of data-intensive applications. In this paper, we propose a novel Hotspot-Aware Manager (HAM) infrastructure for 3D-stacked memory devices capable of optimizing memory access streams via request aggregation, hotspot detection, and in-memory prefetching. %and an associated hotspot-aware page policy. We present the HAM design and implementation, and simulate it on a system using RISC-V embedded cores with attached HMC devices. We extensively evaluate HAM with over 12 benchmarks and applications representing diverse irregular memory access patterns. The results show that, on average, HAM reduces redundant requests by 37.51\% and increases the prefetch buffer hit rate by 4.2 times, compared to a baseline streaming prefetcher. On the selected benchmark set, HAM provides performance gains of 21.81\% in average (up to 34.28\%) and power savings of 35.07\% over a standard 3D-stacked memory.

Wang, Xi↗

DOE OSTI2023

Method and apparatus of integrating memory stacks

A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

Yudanov, Dmitri↗

DOE OSTI2016

Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm{sup 2} after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2019

Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications

Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.

Peng, Ivy Bo↗

DOE OSTI2019

Extreme-bandwidth scalable performance-per-watt GPU architecture

A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design

In recent years, the CNNs have achieved great successes in the image processing tasks, e.g., image recognition and object detection. Unfortunately, traditional CNN's classication is found to be easily misled by increasingly complex image features due to the usage of pooling operations, hence unable to preserve accurate position and pose information of the objects. To address this challenge, a novel neural network structure called Capsule Network has been proposed, which introduces equivariance through capsules to signicantly enhance the learning ability for image segmentation and object detection. Due to its requirement of performing a high volume of matrix operations, CapsNets have been generally accelerated on modern GPU platforms that provide highly optimized software library for common deep learning tasks. However, based on our performance characterization on modern GPUs, CapsNets exhibit low effciency due to the special program and execution features of their routing procedure, including massive unshareable intermediate variables and intensive syn- chronizations, which are very dicult to optimize at software level. To address these challenges, we propose a hybrid computing architecture design named PIM-CapsNet. It preserves GPU's on-chip computing capability for accelerating CNN types of layers in CapsNet, while pipelining with an off-chip in-memory acceleration solution that effectively tackles routing procedure's ineffciency by leveraging the processing-in-memory capability of today's 3D stacked memory. Using routing procedure's inherent parallellization feature, our design enables hierarchical improvements on CapsNet inference effciency through minimizing data movement and maximizing parallel processing in memory. Evaluation results demonstrate that our proposed design can achieve substantial improvement on both performance and energy savings for CapsNet inference, with almost zero accuracy loss. The results also suggest good performance scalability in optimizing the routing procedure with increasing network size.

Zhang, Xingyao↗

DOE OSTI2017

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPU for efficient 3D rendering.

Innovative hardware/software co-design↗

DOE OSTI2019

PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations

Stencil computation is a classic computational kernel present in many high-performance scientific applications, like image process- ing and partial differential equation solvers (PDE). A stencil compu- tation sweeps over a multi-dimensional grid and repeatedly updates values associated with points using the values from neighboring points. Stencil computations often employ large datasets that ex- ceed cache capacity, leading to excessive accesses to the memory subsystem. As such, 3D stencil computations on large grid sizes are memory-bound. In this paper we present PIMS, an in-memory accelerator for stencil computations. PIMS, implemented in the logic layer of a 3D- stacked memory, exploits the high bandwidth provided by through- silicon vias to reduce redundant memory traffic. Our comprehensive evaluation using three different grid sizes with six categories of orders indicate that the proposed architecture reduces 48.25% of data movement on average and obtains up to 65.55% of bank conflict reduction.

Li, Jie↗

DOE OSTI2016

Low-temperature atomic layer deposition of TiO{sub 2} thin layers for the processing of memristive devices

Atomic layer deposition (ALD) represents one of the most fundamental techniques capable of satisfying the strict technological requirements imposed by the rapidly evolving electronic components industry. The actual scaling trend is rapidly leading to the fabrication of nanoscaled devices able to overcome limits of the present microelectronic technology, of which the memristor is one of the principal candidates. Since their development in 2008, TiO{sub 2} thin film memristors have been identified as the future technology for resistive random access memories because of their numerous advantages in producing dense, low power-consuming, three-dimensional memory stacks. The typical features of ALD, such as self-limiting and conformal deposition without line-of-sight requirements, are strong assets for fabricating these nanosized devices. This work focuses on the realization of memristors based on low-temperature ALD TiO{sub 2} thin films. In this process, the oxide layer was directly grown on a polymeric photoresist, thus simplifying the fabrication procedure with a direct liftoff patterning instead of a complex dry etching process. The TiO{sub 2} thin films deposited in a temperature range of 120–230 °C were characterized via Raman spectroscopy and x-ray photoelectron spectroscopy, and electrical current–voltage measurements taken in voltage sweep mode were employed to confirm the existence of resistive switching behaviors typical of memristors. These measurements showed that these low-temperature devices exhibit an ON/OFF ratio comparable to that of a high-temperature memristor, thus exhibiting similar performances with respect to memory applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2024

Dynamic data-driven multiscale modeling for predicting the degradation of a 316L stainless steel nuclear cladding material

Here, we have developed a long short-term memory stacked ensemble (LSTM-SE) surrogate modeling approach that can provide rapid predictions of microstructural evolution and the resultant mechanical properties of American Iron and Steel Institute (AISI) 316L series stainless steel (316LSS) fuel cladding under conditions of varying temperature and radiation dose rate. To acquire training data, we developed and implemented a kinetic Monte Carlo (KMC) model to simulate precipitation kinetics of M 23 C 6 , γ', and G phases within SS316L cladding. Experimentally reported precipitation kinetics of SS316L in literature were linked to the kinetic parameters of the simulated precipitation in our KMC model. The model was then used to simulate microstructure evolution under synthetically generated treatments of varying temperature and radiation dose rate, for periods of up to 3000 hours. Changes in volume fraction, number density, and particle size of precipitates were recorded, and particle area fractions were correlated using statistical methods to develop the surrogate model. Simultaneously, the mechanical properties of the simulated microstructures were evaluated using microstructure-based finite element method (FEM) analysis to determine the elastic modulus, yield stress, ultimate tensile strength, and elongation to failure of the aged microstructures. Using this approach, our surrogate model can predict precipitation behavior within 0.25% volume fraction and mechanical properties within 6% relative error from the values predicted by the KMC and FEM models using 50 training simulations as input. The trained recurrent neural network-based model can return estimations of precipitation kinetics and mechanical properties ~1000 times faster than the physics-based codes. This work demonstrates, as a proof of concept, that reactor material service lifetimes under variable service conditions can be predicted for a statistics-based model from a practicably obtainable dataset.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Dynamic Data-Driven Multiscale Modeling for Predicting Microstructure and Mechanical Properties of 316L Stainless Steel

We have developed a long short-term memory stacked ensemble (LSTM-SE) surrogate modeling approach that can provide rapid predictions of microstructural evolution and the resultant mechanical properties of American Iron and Steel Institute (AISI) 316L series stainless steel (316LSS) fuel cladding under conditions of varying temperature and radiation dose rate. To acquire training data, we developed and implemented a kinetic Monte Carlo (KMC) model to simulate precipitation kinetics of M 23 C 6 , γ', and G phases within SS316L cladding. Experimentally reported precipitation kinetics of SS316L in literature were linked to the kinetic parameters of the simulated precipitation in our KMC model. The model was then used to simulate microstructure evolution under synthetically generated treatments of varying temperature and radiation dose rate, for periods of up to 3000 hours. Changes in volume fraction, number density, and particle size of precipitates were recorded, and particle area fractions were correlated using statistical methods to develop the surrogate model. Simultaneously, the mechanical properties of the simulated microstructures were evaluated using microstructure-based finite element method (FEM) analysis to determine the elastic modulus, yield stress, ultimate tensile strength, and elongation to failure of the aged microstructures. Using this approach, our surrogate model can predict precipitation behavior within 0.25% volume fraction and mechanical properties within 6% relative error from the values predicted by the KMC and FEM models using 50 training simulations as input. The trained recurrent neural network-based model can return estimations of precipitation kinetics and mechanical properties ~1000 times faster than the physics-based codes. This work demonstrates, as a proof of concept, that reactor material service lifetimes under variable service conditions can be predicted for a statistics-based model from a practicably obtainable dataset.

36 MATERIALS SCIENCE↗

DOE OSTI2020

Berry curvature memory through electrically driven stacking transitions

In two-dimensional layered quantum materials, the interlayer stacking order determines both crystalline symmetry and quantum electronic properties such as Berry curvature, topology and electron correlation. Electrical stimuli can strongly influence quasi-particle interactions and the free energy landscape, thus making it possible to access hidden stacking orders with novel quantum properties and enabling dynamic engineering of these attributes. In this paper, we demonstrate electrically driven stacking transitions and a new type of nonvolatile memory based on Berry curvature in few-layer WTe 2 . The interplay of out-of-plane electric fields and electrostatic doping controls in-plane interlayer sliding and creates multiple polar and centrosymmetric stacking orders. In-situ nonlinear Hall transport reveals such stacking rearrangements result in a layer-parity-selective Berry curvature memory in momentum space, where the sign reversal of the Berry curvature only occurs in odd layer crystals. Our findings open an avenue towards exploring coupling between topology, electron correlations, and ferroelectricity in hidden stacking orders and demonstrate a new low energy cost, electrically-controlled topological memory in the atomically thin limit.

36 MATERIALS SCIENCE↗

DOE OSTI2015

In-Memory Data Rearrangement for Irregular, Data-Intensive Computing

The data rearrangement engine (DRE) performs in-memory data restructuring to accelerate irregular, data-intensive applications. An emulation on a field-programmable gate array demonstrates how the DRE could improve speedup, memory bandwidth, and energy consumption on three representative benchmarks.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Geant4 Computing Performance Benchmarking and Monitoring

Performance evaluation and analysis of large scale computing applications is essential for optimal use of resources. As detector simulation is one of the most compute intensive tasks and Geant4 is the simulation toolkit most widely used in contemporary high energy physics (HEP) experiments, it is important to monitor Geant4 through its development cycle for changes in computing performance and to identify problems and opportunities for code improvements. All Geant4 development and public releases are being profiled with a set of applications that utilize different input event samples, physics parameters, and detector configurations. Results from multiple benchmarking runs are compared to previous public and development reference releases to monitor CPU and memory usage. Observed changes are evaluated and correlated with code modifications. Besides the full summary of call stack and memory footprint, a detailed call graph analysis is available to Geant4 developers for further analysis. The set of software tools used in the performance evaluation procedure, both in sequential and multi-threaded modes, include FAST, IgProf and Open|Speedshop. In conclusion, the scalability of the CPU time and memory performance in multi-threaded application is evaluated by measuring event throughput and memory gain as a function of the number of threads for selected event samples.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Stacked filters: learning to filter by structure

We present Stacked Filters, a new probabilistic filter which is fast and robust similar to query-agnostic filters (such as Bloom and Cuckoo filters), and at the same time brings low false positive rates and sizes similar to classifier-based filters (such as Learned Filters). The core idea is that Stacked Filters incorporate workload knowledge about frequently queried non-existing values. Instead of learning, they structurally incorporate that knowledge using hashing and several sequenced filter layers, indexing both data and frequent negatives. Stacked Filters can also gather workload knowledge on-the-fly and adaptively build the filter. We show experimentally that for a given memory budget, Stacked Filters achieve end-to-end query throughput up to 130x better than the best alternative for a workload, either query-agnostic or classifier-based filters, and depending on where data is (SSD or HDD).

Computer Science↗

DOE OSTI2021

Stacking-engineered ferroelectricity in bilayer boron nitride

Stacking a ferroelectric Properties of layered van der Waals structures can depend sensitively on the stacking arrangement of constituent layers. This phenomenon has been exploited to engineer superconducting, correlated insulator, and magnetic states. Two groups now show that ferroelectricity can also be engineered through stacking: Parallel-stacked bilayers of hexagonal boron nitride exhibit ferroelectric switching even though the bulk material is not ferroelectric (see the Perspective by Tsymbal). To explore these phenomena, Yasuda et al. used transport measurements, whereas Vizner Stern et al. focused on atomic force microscopy. Science , abd3230 and abe8177, this issue p. 1458 and p. 1462 ; see also abi7296, p. 1389

Science & Technology - Other Topics↗