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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Frontier system-on-chip (SoC) technology for microwave diagnostics (invited)

The next generation of fusion reactors, exemplified by projects such as the Demonstration Power Plant following the International Thermonuclear Experimental Reactor, faces the monumental challenge of proving the viability of generating electricity through thermonuclear fusion. This pursuit introduces heightened complexities in diagnostic methodologies, particularly in microwave-based diagnostics. The increased neutron fluence necessitates significant reductions in vessel penetrations and the elimination of internal diagnostics, posing substantial challenges. SoC technology offers a promising solution by enabling the miniaturization, modularization, integration, and enhancing the reliability of microwave systems. After seven years of research, our team successfully pioneered the V- and W-band system-on-chip approach, leading to the development of active transmitters and passive receiver modules applied in practical settings, notably within the DIII-D tokamak project. Arrays of these modules have supported microwave imaging diagnostics. New physics measurement results from the Electron Cyclotron Emission Imaging system on DIII-D provide compelling evidence of improved diagnostics following the adoption of SoC technology. Furthermore, we achieved a breakthrough in developing an F-band SoC, advancing higher frequency capabilities for fusion devices. These achievements represent a significant leap forward in fusion diagnostic technology, marking substantial progress toward establishing reliable and efficient plasma diagnostics for future fusion reactors.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2021

Toward Performance Portable Programming for Heterogeneous System-on-Chips: Case Study with Qualcomm Snapdragon SoC

Future heterogeneous Domain-Specific System-on-Chips (DSSoC) will be extraordinarily complex in terms of processors, memory hierarchies, and interconnection networks.To manage this complexity, architects, system software designers, and application developers need programming technologies that are flexible, accurate, efficient, and productive. These technologies will need to be as independent of any one specific architecture as is practical, because the sheer dimensionality and scale of the complexity will not allow porting and optimizing applications foreach given DSSoC. To address these issues, we are developing Cosmic Castle, a performance portable programming toolchain for streaming applications on heterogeneous architectures. The primary focus of Cosmic Castle is on enabling efficient and performant code generation through the smart compiler and intelligent runtime system. This paper presents the preliminary evaluation of our ongoing work toward Cosmic Castle. Specifically, we detail our code porting efforts and evaluate various benchmarks on the Qualcomm Snapdragon SoC using tools developed through Cosmic Castle.

Cabrera, Anthony↗
DOE OSTI2022

A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization

A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.

self-powered IoT system-on-chip (SoC)↗
DOE OSTI2020

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗
DOE OSTI2020

W-band system-on-chip electron cyclotron emission imaging system on DIII-D

Monolithic, millimeter wave “system-on-chip” (SoC) technology has been employed in heterodyne receiver integrated circuit radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature profile and fluctuation evolution diagnostics. Here, a prototype module operating in E-band (72-80 GHz) was first employed in a 2 x 10 element array that demonstrated significant improvements over the previous quasi-optical Schottky diode mixer arrays during the 2018 operational campaign of the DIII-D tokamak. For compatibility with International Thermonuclear Experimental Reactor (ITER) relevant scenarios on DIII-D, the SoC ECEI system was upgraded with 20 horn-waveguide receiver modules. Each individual module contains a University of California at Davis designed W-band (75 -110 GHz) receiver die that integrates a broadband low noise amplifier (LNA), a double balanced down-converting mixer, and a x4 multiplier on the local oscillator (LO) chain. A x2 multiplier and two IF amplifiers are packaged and selected to further boost the signal strength as well as downconvert the signal frequency. The upgraded W-band array exhibits > 30 dB additional gain and 20x improvement in noise temperature comparing with the previous Schottky diode radio frequency (RF) mixer input systems; an internal 8 times multiplier chain is used to bring down the LO frequency below 12 GHz, thereby obviating the need for a large aperture for quasi-optical LO coupling and replacing it with coaxial connectors. The horn-waveguide shielding housing avoids out-of-band noise interference on each individual module. The upgraded ECEI system plays an important role for absolute electron temperature evolution and fluctuation measurements for edge and core region transport physics studies.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2020

MEPHESTO: Modeling Energy-Performance in Heterogeneous SoCs and Their Trade-Offs

Integrated shared memory heterogeneous architectures are pervasive because they satisfy the diverse needs of mobile, autonomous, and edge computing platforms. Although specialized processing units (PUs) that share a unified system memory improve performance and energy efficiency by reducing data movement, they also increase contention for this memory since the PUs interact with each other. Prior work has investigated performance degradation due to memory contention, but few have studied the relationship of power and energy to memory contention. Moreover, a comprehensive solution that models memory contention for kernel placement on contemporary heterogeneous systems on chip (SoCs) in response to energy and performance has been largely unaddressed.This paper presents MEPHESTO, a novel and holistic approach for managing this balance. The authors characterize applications and PUs in terms of two memory contention factors - time factors and power factors - to achieve the desired trade-off between energy and performance for collocated kernel execution on heterogeneous systems. The authors believe that this investigation is the first to combine all of these factors and present a simple knob-based approach that expresses the target trade-off. The approach is evaluated on a diverse integrated shared memory heterogeneous system with a CPU, GPU, and programmable vision accelerator. By using an empirical model for memory contention that provides up to 92% accuracy, the kernel collocation approach can provide a near-optimal ordering and placement based on the user-defined, energy-performance trade-off parameter. Moreover, the dynamic programming-based heuristics provide up to 30% better energy or 20% performance benefits when compared with the greedy approaches commonly employed by previous studies.

Alaul haque monil, Mohammad↗
DOE OSTI2024

Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance Computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

Li, Yuke↗
DOE OSTI2020

OpenSNAPI: Toward a Unified API for SmartNICs

The end of Moore’s Law and Dennard Scaling has produced a renaissance in the field of computer architecture. Unable to continue leveraging silicon-level processor improvements to further enhance performance and scalability, system architects have been forced to explore other options. In this new era of heterogeneous architectures and hardware/software codesign, a new class of devices known as “accelerators” has emerged. Independently designed for optimized execution of distinct workloads, these devices have proven critical to the continued advancement of application performance. SmartNICs, accelerator devices integrated with a network controller, have conventionally been utilized to offload low-level networking functionality. However, newer SmartNIC variants, which incorporate a system-on-chip (SoC) with traditional designs, are challenging this precedent. Leveraging significantly augmented resources, these new devices offer increased versatility and the potential to more effectively complement a given architecture’s CPU. In this talk, we introduce the motivation underlying acceleration, explore the fundamentals of SmartNICs, and discuss traditional use cases. We also detail our initial efforts to investigate the feasibility and benefits of SmartNICs as general-purpose accelerators. We present the OpenSNAPI project created to define a uniform application programming interface (API) for this emerging class of devices. Finally, we provide a brief tutorial regarding development of SmartNIC-accelerated applications on Los Alamos National Laboratory’s SmartNIC-enabled platforms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

A Path Toward Understanding the Performance Capabilities of SmartNIC Devices [Slides]

SmartNICs, accelerator devices integrated with a network, have conventionally been utilized to offload low-level networking functionality. However, newer SmartNIC variants, which incorporate a system-on-chip (SoC) with traditional designs, are challenging this precedent. Leveraging significantly augmented resources, these new devices offer increased versatility and the potential to more effectively complement a given architecture’s CPU. Naturally, there is performance overhead associated with offloading tasks from a host CPU to a SmartNIC. As SmartNICs become more versatile and are used for a wider range of computational tasks, it is critical to understand how well the SmartNICs perform those respective tasks in order to determine whether the cost of offloading is worthwhile. In this work, we lay out a path to understand the important question of when and when not to offload to SmartNIC devices by way of a series of microbenchmarks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

An Experimental Feasibility Study on Applying Neutron Tomography to Encapsulated Spent Nuclear Fuel - 20050

Visual inspection makes easier to ensure the integrity and safety of spent nuclear fuel (SNF) than any classical techniques. Various classical techniques have been applied but there are no reliable methods to qualitatively and quantitatively verify spent fuel in dry storage. Thus, the present authors have developed the prototype safeguards apparatus for dry storage employing the array of He-4 gas scintillation detectors (S670E, Arktis Radiation Detectors Ltd., Switzerland), newly designed to simultaneously measure thermal and fast neutrons without any moderators. The S670E detector has a cylindrical shape with a diameter of 52 mm and active length of 600 mm (total length: 875 mm). The detector is filled by He-4 gas with an approximate pressure of 180 bar for fast neutron detection, and its inner wall is coated by Li-6 for thermal neutron detection. The scintillation lights generated via Li-6 nuclear reaction and elastic scattering are collected by 24 SiPMs linearly paired at the center of the detector. The detector delivers a TTL (Transistor-Transistor Logic) output for pulse readout and UART (Universal Asynchronous Receiver Transmitter) for device control. In order to assess feasibility of the apparatus, an experimental system has been designed, built, and optimized via computational studies. Cf-252 neutron sources and linearly arrayed detectors, working as a single detector, were occupied for this study due to the difficulties in working with SNF. The laboratory scale cask (diameter: 0.67 m, height: 1.5 m), minimized by a factor of 10 compared to the actual thickness of a commercial TN-32 cask, was also manufactured. The detector array was designed to rotate the lab-scale cask and obtain 36 image profiles at every 10 degrees. All profiles were aligned in single frame image called a sinogram, and the cross-sectional image was then fabricated by the inverse radon transform algorithm. These experiments have been repeated with different configurations and numbers of sources. Some gamma-ray sources were also measured with neutron sources in order to distinguish between neutron and gamma-ray pulses. Basically, a He-4 detector is designed to run on Linux OS so it is difficult to directly apply to Windows-based equipment widely used in S. Korea. Therefore, a new data acquisition board working on Windows OS was designed and built. The board mainly consists of FPGA (Field Programmable Gate Array) and SoC (System on Chip) for TTL pulse readout, sorting measured data, and transferring data to a user interface. In conclusion, the tomographic system at lab-scale has shown considerable potential to detect a partial or gross defect of encapsulated assemblies in dry storage. Next steps of this study will be to 1) repeatedly carry out experiments to demonstrate scientific reliability and validity, and 2) numerically integrate signals with weight factors to enhance the image quality since the suggested system based on passive interrogation method requires longer measurement time. Finally, the system will apply to a commercial dry storage phased out soon in S. Korea. (authors)

07 ISOTOPE AND RADIATION SOURCES↗
DOE OSTI2022

Runtime Systems for Energy Efficiency in Advanced Computing Systems

As heterogeneous systems become increasingly popular for both mobile and high-performance computing, conventional efficiency techniques such as dynamic voltage and frequency scaling (DVFS) fail to account for the tightly coupled and varied nature of systems on a chip (SoCs). In this work, we explore the impact of system unaware DVFS techniques on a mobile SoC under three benchmark suites: Chai, Rodinia, and Antutu. We then analyze performance trends across the suites to identify a set of consistent operating points that optimally balance power and performance across the system. The consistent operating points are then constructed into a dependency graph which can be leveraged to produce a more effective, SoC-wide governor.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Hamilton: Flexible, Open Source $10 Wireless Sensor System for Energy Efficient Building Operation

Sensors for improving building performance are rapidly populating the market, driven in part by the drive to reduce greenhouse gas emissions resulting from energy production as well as improve the interior environment for healthy and more productive spaces. UC Berkeley has led wireless sensor development over the past 25 years (e.g., Telos mote), with the Hamilton (named after Alexander Hamilton on the US $10 bill) as the most recent. The Hamilton sensor was designed as a low-cost high-performance sensor that is modular and interoperable. The objective of the Hamilton project was to create, evaluate and establish the technological foundations for secure and easy to deploy building energy efficiency applications utilizing pervasive, low-cost wireless sensors integrated with traditional Building Management Systems (BMS), consumer-sector building components, and powerful data analytics. The project included iterative hardware design, incorporating a high-performance database (BTrDb, http://btrdb.io/), creating and iterating the development of secure data middleware (BOSSwave, WAVE/WAVEMQ), working with and pushing the development of an open-source tiny operating system RiotOS, and implementing and improving protocols such as Thread/OpenThread and TCP/IP. The hardware benefited from careful design to drive down the cost; the design included a System-on-a-Chip (SoC), chip antenna, single crystal and five passive components. Careful design of the operating system created a low-power design to enable a long life with small batteries. The hardware included several sensors: temperature, radiant temperature, relative humidity, magnetometer, accelerometer, and light, with an optional occupancy (Passive InfraRed) sensor. The project was the basis of several applications, both internal to the research team and other researchers and professionals at other institutions. Several applications used the sensor hardware as the basis for other complex devices. Other applications used the sensors to improve building performance through interoperating with the building Heating Ventilation and Air-Conditioning (HVAC) system, such as using occupancy and/or distributed temperature sensing to reduce HVAC zone energy while still providing thermal comfort and to reduce peak loads in small commercial buildings. We demonstrated cloud-based energy analytics, implemented a schedule and a Model Predictive Controller in a small commercial building to optimize HVAC energy, occupancy and electricity price. Initial integration of these technological innovations was performed through the creation of execution containers containing the WAVE agent and various driver, proxy, or building system function logic. The research added to the understanding of efficient sensor hardware, secure middleware, time-series data management (high performance database), efficient communication protocols, and interoperating with applications and building systems. The project showed the technical effectiveness and economic feasibility of creating a low-cost, modular, and easy-to-deploy sensor. Through conversations with multiple end users, the research team discovered that many customers wanted data management and services in addition to the sensors. HamiltonIOT developed packages of sensors, border router, and data services to provide a seamless “plug-and-play” sensor deployment. Some customers were willing to pay for higher quality sensors (such as light); some customers wanted a robust enclosure (waterproof).

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2026

The future of subsurface monitoring: AEC’s breakthroughs in CCS technology

Carbon capture and storage (CCS) has emerged as a key solution in the fight against climate change. However, for CCS to succeed, it is crucial to ensure that the sequestered CO2 stays safely trapped underground. The U.S. Department of Energy (DOE) has emphasized the need for advancements in subsurface monitoring, measurement, reporting, and verification. Aside from caprock integrity failure, the other primary failure points usually involve defective cement in the casing annulus of wellbores or plugged and abandoned wells. In addition, many energy producers (e.g., oil and gas, geothermal) and storage and disposal operators (e.g., H2 and water) must deal with the same issue. Poorly placed or degraded cement can create pathways for gas or fluid to escape from casing annuli and in plugged and abandoned or orphan wells, posing environmental risks. Yet, a reliable and cost-effective way to monitor cement and well integrity over multiple decades is still unavailable. Traditional geophysical methods like 4D seismic imaging and surface-based electromagnetic monitoring lack the resolution and accuracy for detecting these types of failures (Vasco et al., 2022; Fawad and Mondol, 2021). Wireline logging is expensive to run continuously and is obtrusive to the operation. While fiber optics can potentially be a solution, its bulkiness can significantly compromise the cement's integrity. To address these challenges, the Advanced Energy Consortium (AEC) at The University of Texas at Austin’s Bureau of Economic Geology (the Bureau) has been pioneering research in subsurface monitoring using its portfolio of distributed autonomous microfabricated sensors for harsh subsurface environments since 2008. A class of these microsensors [System on a Chip (SoC)] can be mixed in cement and permanently placed without compromising the cement column; the sensors would then communicate with each other or a data acquisition (DAQ) master node. Another class of the AEC microsensors can be fully autonomous, with rechargeable micro-batteries capable of exceeding 100°C, flash memory, and, currently, a pressure and temperature sensor. They are designed to circulate in mud, geothermal fluids, U-loops, or pipelines. They can log data into memory and are unobtrusive to operations. Our team has been working on a multi-year DOE-funded project (DE-FE0031856)—supported by $2.95M in federal funding and $0.75M in cost-matching from the AEC—to demonstrate SoC sensor utility for CO2 leakage monitoring in CCS applications. This multi-institutional collaboration developed a novel sensing architecture utilizing radiofrequency (RF) microsensors embedded within the cement sheath. These sensors detect CO2 migration and are interrogated via a Smart Casing Collar (SCC).

58 GEOSCIENCES↗
DOE OSTI2020

Software-Defined Ultrasonic Communication System Based on Time-reversal Signal Processing

Ultrasonic communication through solid channels suffers from channel dispersion, attenuation, and multipath effect. For example, in elbow shape pipes or complex structures, the elastic waves are reflected and reverberated in multipath resulting in a major dispersion of the signals. In solid channels such as flat bar, multipath propagation is the main reason for bit-wavelet spreading and intersymbol interference (ISI). The conventional modulation method like OOK (on-off-keying) or PSK (phase-shift-keying) fails to provide a useful Signal-to-Noise Ratio (SNR). Time-reversal (TR) signal processing method is a promising technique that can compress the spreading of the bit-wavelet and strengthen the peak signal energy on the receiver. In this study, Finite Element Analysis (FEA) using ABAQUS software tools is used to characterize the bit-wavelet spreading effect caused by dispersive communication channels. Also, this study presents the impact of TR ultrasonic communication as a function of excitation pulse width, channel length, and carrier frequency through a flat-bar channel. A Software-Defined System-on-Chip (SD-SoC) platform is examined as a viable solution for the low-complexity and energy-efficient ultrasonic communication system. The proposed TR based SD-SoC ultrasonic communication system can make full use of signal dispersion for peak performance by minimizing the ISI within a dispersive and reverberant metal channel.

FEM simulation↗
DOE OSTI2025

Radio Frequency Field Programable Gate Array Implementation of Reflectometry Cable Monitoring

This document describes the development of a field programable gate array (FPGA) radio frequency system on a chip (RF SoC) adaptation and evaluation of the single-board device to perform both Frequency Domain Reflectometry (FDR) and Spread Spectrum Time Domain Reflectometry (SSTDR) for offline and online cable testing. The work builds on and leverages the work of Pacific Northwest National Laboratory (PNNL) in airport millimeter wave technology by using the same development hardware employed in that program. The work is performed under sponsorship from the U.S. Department of Energy (DOE) Light Water Reactor Sustainability (LWRS) program and the task objective is to confirm and demonstrate feasibility to adapt FPGA technology for a cost-effective multiplexed single-board electronic module to perform cable tests that are equivalent to commercial and laboratory test instruments for FDR and SSTDR cable tests. The developed 2-channel (extendable to 7 channels) system was compared to dedicated and proven test instruments and shown to produce equivalent results on a range of cables and with a range of damage types. The FPGA reflectometry test board is one of several technologies that could facilitate implementation of online monitoring of safety critical cable systems.

42 ENGINEERING↗
DOE OSTI2025

Passband Signal Detection at the Edge

Algorithms for radio frequency (RF) spectrum awareness need to be compatible with edge hardware to be practical for many applications. We developed a signal detection and classification model for the ZCU111 RF System-on-a-Chip (RFSoC) that operates on the fast Fourier transform of passband RF data. The system can detect and classify multiple signals of interest and display the predictions in real-time. The model consists of a modified ConvNeXt backbone and YOLOv3 head to operate on the Deep Learning Processing Unit on the RFSoC. We gathered datasets for training and testing by using a software defined radio to transmit example signals of Wi-Fi 802.11 b/g, Wi-Fi 802.11 n, FM Radio, LTE and LTE-M. By leveraging multiple inputs on the RFSoC frontend, the datasets span up to 4 GHz of bandwidth. The models showed high performance in classification accuracy, center frequency error, bandwidth error, and detection accuracy for both single and multi-signal datasets.

42 ENGINEERING↗