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14 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Frontier system-on-chip (SoC) technology for microwave diagnostics (invited)

The next generation of fusion reactors, exemplified by projects such as the Demonstration Power Plant following the International Thermonuclear Experimental Reactor, faces the monumental challenge of proving the viability of generating electricity through thermonuclear fusion. This pursuit introduces heightened complexities in diagnostic methodologies, particularly in microwave-based diagnostics. The increased neutron fluence necessitates significant reductions in vessel penetrations and the elimination of internal diagnostics, posing substantial challenges. SoC technology offers a promising solution by enabling the miniaturization, modularization, integration, and enhancing the reliability of microwave systems. After seven years of research, our team successfully pioneered the V- and W-band system-on-chip approach, leading to the development of active transmitters and passive receiver modules applied in practical settings, notably within the DIII-D tokamak project. Arrays of these modules have supported microwave imaging diagnostics. New physics measurement results from the Electron Cyclotron Emission Imaging system on DIII-D provide compelling evidence of improved diagnostics following the adoption of SoC technology. Furthermore, we achieved a breakthrough in developing an F-band SoC, advancing higher frequency capabilities for fusion devices. These achievements represent a significant leap forward in fusion diagnostic technology, marking substantial progress toward establishing reliable and efficient plasma diagnostics for future fusion reactors.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2022

A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization

A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.

self-powered IoT system-on-chip (SoC)↗
DOE OSTI2020

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗
DOE OSTI2021

Toward Performance Portable Programming for Heterogeneous System-on-Chips: Case Study with Qualcomm Snapdragon SoC

Future heterogeneous Domain-Specific System-on-Chips (DSSoC) will be extraordinarily complex in terms of processors, memory hierarchies, and interconnection networks.To manage this complexity, architects, system software designers, and application developers need programming technologies that are flexible, accurate, efficient, and productive. These technologies will need to be as independent of any one specific architecture as is practical, because the sheer dimensionality and scale of the complexity will not allow porting and optimizing applications foreach given DSSoC. To address these issues, we are developing Cosmic Castle, a performance portable programming toolchain for streaming applications on heterogeneous architectures. The primary focus of Cosmic Castle is on enabling efficient and performant code generation through the smart compiler and intelligent runtime system. This paper presents the preliminary evaluation of our ongoing work toward Cosmic Castle. Specifically, we detail our code porting efforts and evaluate various benchmarks on the Qualcomm Snapdragon SoC using tools developed through Cosmic Castle.

Cabrera, Anthony↗
DOE OSTI2020

W-band system-on-chip electron cyclotron emission imaging system on DIII-D

Monolithic, millimeter wave “system-on-chip” (SoC) technology has been employed in heterodyne receiver integrated circuit radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature profile and fluctuation evolution diagnostics. Here, a prototype module operating in E-band (72-80 GHz) was first employed in a 2 x 10 element array that demonstrated significant improvements over the previous quasi-optical Schottky diode mixer arrays during the 2018 operational campaign of the DIII-D tokamak. For compatibility with International Thermonuclear Experimental Reactor (ITER) relevant scenarios on DIII-D, the SoC ECEI system was upgraded with 20 horn-waveguide receiver modules. Each individual module contains a University of California at Davis designed W-band (75 -110 GHz) receiver die that integrates a broadband low noise amplifier (LNA), a double balanced down-converting mixer, and a x4 multiplier on the local oscillator (LO) chain. A x2 multiplier and two IF amplifiers are packaged and selected to further boost the signal strength as well as downconvert the signal frequency. The upgraded W-band array exhibits > 30 dB additional gain and 20x improvement in noise temperature comparing with the previous Schottky diode radio frequency (RF) mixer input systems; an internal 8 times multiplier chain is used to bring down the LO frequency below 12 GHz, thereby obviating the need for a large aperture for quasi-optical LO coupling and replacing it with coaxial connectors. The horn-waveguide shielding housing avoids out-of-band noise interference on each individual module. The upgraded ECEI system plays an important role for absolute electron temperature evolution and fluctuation measurements for edge and core region transport physics studies.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance Computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

Li, Yuke↗
DOE OSTI2020

OpenSNAPI: Toward a Unified API for SmartNICs

The end of Moore’s Law and Dennard Scaling has produced a renaissance in the field of computer architecture. Unable to continue leveraging silicon-level processor improvements to further enhance performance and scalability, system architects have been forced to explore other options. In this new era of heterogeneous architectures and hardware/software codesign, a new class of devices known as “accelerators” has emerged. Independently designed for optimized execution of distinct workloads, these devices have proven critical to the continued advancement of application performance. SmartNICs, accelerator devices integrated with a network controller, have conventionally been utilized to offload low-level networking functionality. However, newer SmartNIC variants, which incorporate a system-on-chip (SoC) with traditional designs, are challenging this precedent. Leveraging significantly augmented resources, these new devices offer increased versatility and the potential to more effectively complement a given architecture’s CPU. In this talk, we introduce the motivation underlying acceleration, explore the fundamentals of SmartNICs, and discuss traditional use cases. We also detail our initial efforts to investigate the feasibility and benefits of SmartNICs as general-purpose accelerators. We present the OpenSNAPI project created to define a uniform application programming interface (API) for this emerging class of devices. Finally, we provide a brief tutorial regarding development of SmartNIC-accelerated applications on Los Alamos National Laboratory’s SmartNIC-enabled platforms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

A Path Toward Understanding the Performance Capabilities of SmartNIC Devices [Slides]

SmartNICs, accelerator devices integrated with a network, have conventionally been utilized to offload low-level networking functionality. However, newer SmartNIC variants, which incorporate a system-on-chip (SoC) with traditional designs, are challenging this precedent. Leveraging significantly augmented resources, these new devices offer increased versatility and the potential to more effectively complement a given architecture’s CPU. Naturally, there is performance overhead associated with offloading tasks from a host CPU to a SmartNIC. As SmartNICs become more versatile and are used for a wider range of computational tasks, it is critical to understand how well the SmartNICs perform those respective tasks in order to determine whether the cost of offloading is worthwhile. In this work, we lay out a path to understand the important question of when and when not to offload to SmartNIC devices by way of a series of microbenchmarks.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Passband Signal Detection at the Edge

Algorithms for radio frequency (RF) spectrum awareness need to be compatible with edge hardware to be practical for many applications. We developed a signal detection and classification model for the ZCU111 RF System-on-a-Chip (RFSoC) that operates on the fast Fourier transform of passband RF data. The system can detect and classify multiple signals of interest and display the predictions in real-time. The model consists of a modified ConvNeXt backbone and YOLOv3 head to operate on the Deep Learning Processing Unit on the RFSoC. We gathered datasets for training and testing by using a software defined radio to transmit example signals of Wi-Fi 802.11 b/g, Wi-Fi 802.11 n, FM Radio, LTE and LTE-M. By leveraging multiple inputs on the RFSoC frontend, the datasets span up to 4 GHz of bandwidth. The models showed high performance in classification accuracy, center frequency error, bandwidth error, and detection accuracy for both single and multi-signal datasets.

42 ENGINEERING↗
DOE OSTI2020

Software-Defined Ultrasonic Communication System Based on Time-reversal Signal Processing

Ultrasonic communication through solid channels suffers from channel dispersion, attenuation, and multipath effect. For example, in elbow shape pipes or complex structures, the elastic waves are reflected and reverberated in multipath resulting in a major dispersion of the signals. In solid channels such as flat bar, multipath propagation is the main reason for bit-wavelet spreading and intersymbol interference (ISI). The conventional modulation method like OOK (on-off-keying) or PSK (phase-shift-keying) fails to provide a useful Signal-to-Noise Ratio (SNR). Time-reversal (TR) signal processing method is a promising technique that can compress the spreading of the bit-wavelet and strengthen the peak signal energy on the receiver. In this study, Finite Element Analysis (FEA) using ABAQUS software tools is used to characterize the bit-wavelet spreading effect caused by dispersive communication channels. Also, this study presents the impact of TR ultrasonic communication as a function of excitation pulse width, channel length, and carrier frequency through a flat-bar channel. A Software-Defined System-on-Chip (SD-SoC) platform is examined as a viable solution for the low-complexity and energy-efficient ultrasonic communication system. The proposed TR based SD-SoC ultrasonic communication system can make full use of signal dispersion for peak performance by minimizing the ISI within a dispersive and reverberant metal channel.

FEM simulation↗
DOE OSTI2022

System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗