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Results for “Temporal Logic”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Voltage Restoration in Microgrids using Temporal Logic Specifications

This paper proposes an energy storage controller synthesis method for voltage restoration in microgrids with respect to temporal logic specifications (TLSs). TLSs is introduced in this paper as a formalism to control the voltage variation of a critical bus against an operational bounds over time. The power system with synchronous generator (SG) connected to a critical load bus is modeled as a set of differential-algebraic equations and a simplified analytical model is derived to describe the voltage variation of this critical bus. The control objective is to schedule an optimal control input signal from a supportive energy storage system (ESS) connected to the critical bus, such that the voltage variation of the latter satisfies the TLSs, such as a finite-time restoration. The proposed control is verified on a lumped distribution system model. With this control diagram, supportive controllers can be designed to make voltage behaviors comply with grid codes and avoid unnecessary relay actions.

Taousser, Fatima Zohra↗
NASA NTRS1990

The Temporal Logic of the Tower Chief System

The purpose is to describe the logic used in the reasoning scheme employed in the Tower Chief system, a runway configuration management system. First, a review of classical logic is given. Defensible logics, truth maintenance, default logic, temporally dependent propositions, and resource allocation and planning are discussed.

Hazelton, Lyman R., Jr.↗
NASA NTRSDate not supplied

Seeing is Believing: Monitoring Future Time Temporal Logic

Runtime monitors for future-time unbounded temporal logics like RVLTL, LTL 3 and FLTL, have double-exponential (2^2^n) worst-case space complexity bounds in size of the input formula. The semantics of these logics require monitors to perform general satisfiability solving for LTL expressions, a well-studied problem whose computational complexity is NP-hard and PSPACE-complete. This paper introduces an unbounded future-time linear temporal logic defined over a lattice. We call our logic an incremental temporal logic as it can be viewed as incrementally constructing proofs about the trace. On this account, we view online runtime monitoring as a decision procedure for proofs systems about incrementally growing traces. We demonstrate that our incremental temporal logic allows monitor construction to void satisfiability solving while still soundly detecting when the property is violated in an online fashion. This enables asymptotic improvements in space complexity. As proof, we provide a procedure to construct monitors that utilize linear space and time in the size of the input formula, while remaining constant in the size of the input stream and suitable for online monitoring. We further demonstrate, through several examples, that our incremental temporal logic is straightforward to adopt and practical for runtime verification.

temporal logic↗
NASA NTRS2018

DejaVu: A Monitoring Tool for First-Order Temporal Logic

Runtime Verification (rv) is aimed at analyzing individual execution traces and temporal behaviors observed from running programs and systems. Its traditional purpose is in detecting the lack of conformance with respect to a formal specification. While very early rv systems were based on specifications given in some form of propositional temporal logic, recent efforts have focused on monitoring so-called parametric specifications over events that carry data. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this paper, we describe our monitoring tool, DejaVu, which implements our algorithm [HPU17] for monitoring first-order past linear-time temporal logic over a sequence of events that carry data. We propose the use of Binary Decision Diagrams (bdds) [Bry86] for representing and manipulating sets of observed data since (1) bdds provide highly compact representations, (2) operations over bdds, in particular complementation, are very efficient, and (3) the monitor construction for the propositional case shown in [HR02] naturally extends to bdds. Our experiments show a substantial improvement in performance compared to a related tool.

Ulus, Dogan↗
NASA NTRS1990

Model checking for linear temporal logic: An efficient implementation

This report provides evidence to support the claim that model checking for linear temporal logic (LTL) is practically efficient. Two implementations of a linear temporal logic model checker is described. One is based on transforming the model checking problem into a satisfiability problem; the other checks an LTL formula for a finite model by computing the cross-product of the finite state transition graph of the program with a structure containing all possible models for the property. An experiment was done with a set of mutual exclusion algorithms and tested safety and liveness under fairness for these algorithms.

Sherman, Rivi↗
NASA NTRS1989

An efficient temporal logic for robotic task planning

Computations required for temporal reasoning can be prohibitively expensive if fully general representations are used. Overly simple representations, such as totally ordered sequence of time points, are inadequate for use in a nonlinear task planning system. A middle ground is identified which is general enough to support a capable nonlinear task planner, but specialized enough that the system can support online task planning in real time. A Temporal Logic System (TLS) was developed during the Intelligent Task Automation (ITA) project to support robotic task planning. TLS is also used within the ITA system to support plan execution, monitoring, and exception handling.

Becker, Jeffrey M.↗
NASA NTRS2001

Synthesizing Dynamic Programming Algorithms from Linear Temporal Logic Formulae

The problem of testing a linear temporal logic (LTL) formula on a finite execution trace of events, generated by an executing program, occurs naturally in runtime analysis of software. We present an algorithm which takes an LTL formula and generates an efficient dynamic programming algorithm. The generated algorithm tests whether the LTL formula is satisfied by a finite trace of events given as input. The generated algorithm runs in linear time, its constant depending on the size of the LTL formula. The memory needed is constant, also depending on the size of the formula.

Rosu, Grigore↗
NASA NTRS2001

Testing Linear Temporal Logic Formulae on Finite Execution Traces

We present an algorithm for efficiently testing Linear Temporal Logic (LTL) formulae on finite execution traces. The standard models of LTL are infinite traces, reflecting the behavior of reactive and concurrent systems which conceptually may be continuously alive. In most past applications of LTL. theorem provers and model checkers have been used to formally prove that down-scaled models satisfy such LTL specifications. Our goal is instead to use LTL for up-scaled testing of real software applications. Such tests correspond to analyzing the conformance of finite traces against LTL formulae. We first describe what it means for a finite trace to satisfy an LTL property. We then suggest an optimized algorithm based on transforming LTL formulae. The work is done using the Maude rewriting system. which turns out to provide a perfect notation and an efficient rewriting engine for performing these experiments.

Havelund, Klaus↗
NASA NTRS2001

Runtime Analysis of Linear Temporal Logic Specifications

This report presents an approach to checking a running program against its Linear Temporal Logic (LTL) specifications. LTL is a widely used logic for expressing properties of programs viewed as sets of executions. Our approach consists of translating LTL formulae to finite-state automata, which are used as observers of the program behavior. The translation algorithm we propose modifies standard LTL to B chi automata conversion techniques to generate automata that check finite program traces. The algorithm has been implemented in a tool, which has been integrated with the generic JPaX framework for runtime analysis of Java programs.

Giannakopoulou, Dimitra↗
DOE OSTI2020

Signal Temporal Logic Control for Residential HVAC Systems to Accommodate High Solar PV Penetration

This paper proposes a new signal temporal logic (STL) control for ON/OFF residential buildings' Heating Ventilation and Air Conditioning (HVAC) systems. STL is used to control indoor temperatures while consuming most of the generated solar photovoltaic (PV) power locally to minimize its impact on the grid and reduce the need for large energy storage devices. In contrast to most, if not all, control mechanisms such as the traditional model predictive control (MPC), STL control allows for including temporal constraints in the control formulation to further relax indoor temperatures' constraints and allow them to exceed the comfort band limits for a prespecified (short) period of time. This relaxation allows to consume an additional PV power by the HVAC systems, which prevents such an unwanted intermittent power from affecting the grid. We formulate the MPC-based STL control mechanism to implement the objective. Simulation results show that the PV tracking performance has been improved while employing the proposed STL controller.

Wu, Tumin↗
DOE OSTI2020

Mitigation of Motor Stalling and FIDVR via Energy Storage Systems with Temporal Logic Specifications

The fault-induced delayed voltage recovery (FIDVR) phenomenon has been very common from the distribution system through the transmission system. It causes a delay on recovering significantly depressed local voltage after the fault is cleared, and it can also lead to more widespread cascading system failures. Mitigating this event with current control approaches is challenging and becoming a crucial issue. Here, a model predictive control-based strategy employing signal temporal logic specifications is proposed to help mitigate FIDVR. To this end, it investigates and extends a dynamic performance model allowing analytic insights into the system-wide impact of motor stalling and FIDVR. The proposed controller provides richer descriptions of voltage specifications addressing both magnitude and time simultaneously. We consider different control specifications with reactive power support from energy storage systems to prevent the voltage during/after the fault from dropping too low, and reduce the delay time of voltage recovery. The simulation results conducted with the IEEE 57 bus test network validate the proposed method and demonstrate the effectiveness of the mitigation strategy on FIDVR.

25 ENERGY STORAGE↗
DOE OSTI2020

Hardware-in-the-loop Testing of Signal Temporal Logic Frequency Control in a Microgrid

This paper presents a hardware-in-the-loop (HITL) testing and lessons learned for a signal temporal logic (STL) frequency control in a microgrid setting. In contrast to most, if not all, traditional control mechanisms, the STL control allows for including temporal constraints in the control formulation to handle sophisticated specifications from grid codes and protection relays. This feature provides richer descriptions of control specifications to address both magnitude and time simultaneously, hence a valuable tool for power system operation and control. An ultra-low voltage (24V) HITL microgrid platform consisting of two type-3 wind turbine generators and one diesel generator is used to test the proposed STL frequency control. In experimental case studies, we demonstrate that the HITL frequency responses closely match the simulated ones and strictly satisfy the designed STL control specifications.

Ferrari Maglia, Max↗
DOE OSTI2020

A phase transition model and temporal logic specifications for smart energy systems - revisited

In this paper, we revisit the method of a phase transition model for representing hybrid systems and temporal logic specifications (TLSs) for specifying desired behaviors of systems, and discuss their usefulness for smart energy systems. On the one hand, the phase transition model incorporates the continuous model of the relay device action with a particular structural form that allows for the construction of a single, global differential-algebraic equation for hybrid systems (thus smoothed hybrid systems). On the other hand, the TLS allows sophisticated descriptions of control specifications addressing both magnitude and time simultaneously, which has recently been applied to the control strategy of several types of continuous and hybrid systems. We provide high-level descriptions of each of the two techniques and present simulation results in the context of smart energy systems.

Park, Byungkwon↗
NASA NTRS2018

Runtime Verification: From Propositional to First-Order Temporal Logic

Runtime Verification is a branch of formal methods concerned with analysis of execution traces for the purpose of determining the state or general quality of the executing system. The field covers numerous approaches, one of which is specification-based runtime verification, where execution traces are checked against formal specifications. The paper presents syntax, semantics, and monitoring algorithms for respectively propositional and first-order temporal logics. In propositional logics the observed events in the execution trace are represented using atomic propositions, while first-order logic allows universal and existential quantification over data occurring as arguments in events. Monitoring of the first-order case is drastically more challenging than the propositional case, and we present a solution for this problem based on BDDs. We furthermore discuss monitorability of temporal properties by dividing them into different classes representing different degrees of monitorability.

Peled, Doron↗
NASA NTRS1990

Decidability for a temporal logic used in discrete-event system analysis

The type of plant considered is one that can be modeled by a nondeterministic finite-state machine P. The regulator is a deterministic finite state machine R. The closed-loop system is formed by connecting P and R in a regulator configuration. Formulas in a propositional temporal language are used to describe the behavior of the closed-loop system. It is shown that there is a mechanical procedure which, for a given P and R, and a temporal formula Psi, will determine in a finite number of steps whether or not Psi must be true. This 'decidability' result could be proven using other known results on temporal logic. The proof given here shows that the behavior of the closed-loop system may safely be assumed to be ultimately periodic. The results are illustrated on two discrete-event system examples.

Knight, J. F.↗
NASA NTRS1989

Temporal logics meet telerobotics

The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.

Rutten, Eric↗
DOE OSTI2020

Model predictive control for voltage restoration in microgrids using temporal logic specifications

Power system operation will encounter numerous voltage variabilities as the proliferation of renewable energy continues. Real-time monitoring and communication technologies can potentially improve voltage stability by enabling the rapid detection of voltage deviations and the implementation of corrective actions. These corrective actions will only be effective in restoring stability if they are chosen in a timely and scalable manner. This paper considers the problem of power systems’ load voltage control in order to simultaneously address both magnitude and time voltage specifications. In order to comply with grid codes and avoid unnecessary relay protection actions, a model predictive control (MPC)-based control strategy employing temporal logic specifications (TLSs) is proposed. The TLSs strategy is introduced as a formalism to control the voltage variation at a critical load bus against operational bounds over time. The control objective is to schedule optimal control input signals from the available supportive energy storage systems, which provide reactive power injections, leading to satisfying the specified finite-time restoration described by the TLSs with minimal control efforts. The simulation results display that the TLSs strategy for power systems’ voltage control synthesis is extremely significant.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2017

First Order Temporal Logic Monitoring with BDDs

Runtime verification is aimed at analyzing execution traces stemming from a running program or system. The traditional purpose is to detect the lack of conformance with respect to a formal specification. Numerous efforts in the field have focused on monitoring so-called parametric specifications, where events carry data, and formulas can refer to such. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of Boolean operators, quantification, and lookup of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this work we explore the use of Binary Decision Diagrams (BDDs) for representing observed data. Our experiments show a substantial improvement in performance compared to related work.

Ulus, Dogan↗