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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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10 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Materials Data on VCo(PO4)2 by Materials Project

VCo(PO4)2 crystallizes in the monoclinic P2_1/m space group. The structure is three-dimensional. V4+ is bonded to six O2- atoms to form distorted VO6 octahedra that share corners with four equivalent CoO6 octahedra, corners with four PO4 tetrahedra, and an edgeedge with one PO4 tetrahedra. The corner-sharing octahedra tilt angles range from 48–49°. There are a spread of V–O bond distances ranging from 1.84–2.10 Å. Co2+ is bonded to six O2- atoms to form CoO6 octahedra that share corners with four equivalent VO6 octahedra, corners with four PO4 tetrahedra, and an edgeedge with one PO4 tetrahedra. The corner-sharing octahedra tilt angles range from 48–49°. There are a spread of Co–O bond distances ranging from 1.98–2.20 Å. There are two inequivalent P5+ sites. In the first P5+ site, P5+ is bonded to four O2- atoms to form PO4 tetrahedra that share a cornercorner with one CoO6 octahedra, corners with three equivalent VO6 octahedra, and an edgeedge with one CoO6 octahedra. The corner-sharing octahedra tilt angles range from 41–55°. There are a spread of P–O bond distances ranging from 1.50–1.59 Å. In the second P5+ site, P5+ is bonded to four O2- atoms to form PO4 tetrahedra that share a cornercorner with one VO6 octahedra, corners with three equivalent CoO6 octahedra, and an edgeedge with one VO6 octahedra. The corner-sharing octahedra tilt angles range from 32–60°. There are a spread of P–O bond distances ranging from 1.50–1.59 Å. There are six inequivalent O2- sites. In the first O2- site, O2- is bonded in a bent 150 degrees geometry to one V4+ and one P5+ atom. In the second O2- site, O2- is bonded in a distorted bent 120 degrees geometry to one Co2+ and one P5+ atom. In the third O2- site, O2- is bonded in a 3-coordinate geometry to one V4+, one Co2+, and one P5+ atom. In the fourth O2- site, O2- is bonded in a 3-coordinate geometry to one V4+, one Co2+, and one P5+ atom. In the fifth O2- site, O2- is bonded in a bent 150 degrees geometry to one V4+ and one P5+ atom. In the sixth O2- site, O2- is bonded in a bent 150 degrees geometry to one Co2+ and one P5+ atom.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Materials Data on VCo by Materials Project

CoV is Tetraauricupride structured and crystallizes in the cubic Pm-3m space group. The structure is three-dimensional. V is bonded in a body-centered cubic geometry to eight equivalent Co atoms. All V–Co bond lengths are 2.51 Å. Co is bonded in a body-centered cubic geometry to eight equivalent V atoms.

36 MATERIALS SCIENCE↗
DOE OSTI2022

A Smart System for the Contactless Measurement of Energy Expenditure

Energy Expenditure (EE) (kcal/day), a key element to guide obesity treatment, is measured from CO 2 production, VCO 2 (mL/min), and/or O 2 consumption, VO 2 (mL/min). Current technologies are limited due to the requirement of wearable facial accessories. A novel system, the Smart Pad, which measures EE via VCO 2 from a room’s ambient CO 2 concentration transients was evaluated. Resting EE (REE) and exercise VCO 2 measurements were recorded using Smart Pad and a reference instrument to study measurement duration’s influence on accuracy. The Smart Pad displayed 90% accuracy (±1 SD) for 14–19 min of REE measurement and for 4.8–7.0 min of exercise, using known room’s air exchange rate. Additionally, the Smart Pad was validated measuring subjects with a wide range of body mass indexes (BMI = 18.8 to 31.4 kg/m2), successfully validating the system accuracy across REE’s measures of ~1200 to ~3000 kcal/day. Furthermore, high correlation between subjects’ VCO 2 and λ for CO 2 accumulation was observed (p < 0.00001, R = 0.785) in a 14.0 m3 sized room. This finding led to development of a new model for REE measurement from ambient CO 2 without λ calibration using a reference instrument. The model correlated in nearly 100% agreement with reference instrument measures (y = 1.06x, R = 0.937) using an independent dataset (N = 56).

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Ultra-broadband voltage-controlled oscillator linearization for frequency modulated continuous wave MMW imaging systems

Millimeter-wave (MMW) imaging systems require high resolution and spurious free dynamic range (SFDR) to produce images with low artifacts. In these systems, lateral resolution is determined by the center frequency and the ratio of the aperture size to the distance to the target. The downrange resolution is determined by the system bandwidth; for very fine downrange resolution of a target, or material layers/discontinuities, the bandwidth must be very broad. Additionally, the response over the bandwidth must be measured very rapidly to support high speed acquisition over large apertures. A voltage-controlled oscillator (VCO) is a standard means of generating the ultra-broadband frequency chirp. This paper investigates the use of a broadband VCO for use in MMW imaging systems, a linear-phase calibration technique, and digital-to-analog converter (DAC) parameter considerations for controlling the VCO.

FMCW, homodyne, VCO, DAC, difference frequency, SF↗
DOE OSTI2020

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process

This paper presents a low jitter dual-path chargepump phase locked loop (PLL) synthesizer in a CMOS 65-nm process for quantum readout applications. The PLL incorporates a programmable dual chargepump and a loop filter with both proportional and integral paths that can be driven independently providing flexible control of the loop bandwidth to achieve low jitter performance. The design is implemented at 300 K and critical blocks like voltage-controlled oscillator (VCO) and chargepump (CP) are analyzed at 77 K based on the characterized results. The LC-VCO is realized with the class-C NMOS only architecture with 5-bit coarse control and quadrature signals are generated with poly phase filter. The VCO is designed with the tuning range of 1 GHz around the center frequency of 6 GHz with Phase Noise of -123 dBc/Hz and -132 dBc/Hz at 1MHz offset at 300 K and 77 K temperature. The simulated PLL rms jitter is 125 fs at 6 GHz with a power consumption of 8 mW at the 1.2 V power supply.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Setup and Testing of PSEC5 ASIC Boards

The PSEC5 ASIC is a high-speed waveform sampling chip developed for precise measurements. This report presents the design review, test board configurations, and results from functional validation of the PSEC5 device. Key aspects examined include power integrity, voltage-controlled oscillator (VCO) behavior, SPI register functionality, clock division characteristics, readout performance, and analog biasing response. Tests were conducted across two boards under varied voltage conditions and signal configurations. Notable observations include robust VCO output, SPI communication irregularities, and anomalous readout conditions. The findings support design iterations for improved ASIC operability and firmware integration.

Fahey, Alexander [North Central Coll.]↗
DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗