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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Soft Real-Time PID Control on a VME Computer

microPID (uPID) is a computer program for real-time proportional + integral + derivative (PID) control of a translation stage in a Fourier-transform ultraviolet spectrometer. microPID implements a PID control loop over a position profile at sampling rate of 8 kHz (sampling period 125microseconds). The software runs in a strippeddown Linux operating system on a VersaModule Eurocard (VME) computer operating in real-time priority queue using an embedded controller, a 16-bit digital-to-analog converter (D/A) board, and a laser-positioning board (LPB). microPID consists of three main parts: (1) VME device-driver routines, (2) software that administers a custom protocol for serial communication with a control computer, and (3) a loop section that obtains the current position from an LPB-driver routine, calculates the ideal position from the profile, and calculates a new voltage command by use of an embedded PID routine all within each sampling period. The voltage command is sent to the D/A board to control the stage. microPID uses special kernel headers to obtain microsecond timing resolution. Inasmuch as microPID implements a single-threaded process and all other processes are disabled, the Linux operating system acts as a soft real-time system.

Karayan, Vahag↗
NASA NTRS1992

VME rollback hardware for time warp multiprocessor systems

The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

Robb, Michael J.↗
NASA NTRS1997

Development of a Production Ready Automated Wire Delivery System

The current development effort is a Phase 3 research study entitled "A Production Ready Automated Wire Delivery System", contract number NAS8-39933, awarded to Nichols Research Corporation (NRC). The goals of this research study were to production harden the existing Automated Wire Delivery (AWDS) motion and sensor hardware and test the modified AWDS in a range of welding applications. In addition, the prototype AWDS controller would be moved to the VME bus platform by designing, fabricating and testing a single board VME bus AWDS controller. This effort was to provide an AWDS that could transition from the laboratory environment to production operations. The project was performed in two development steps. Step 1 modified and tested an improved MWG. Step 2 developed and tested the AWDS single board VME bus controller. Step 3 installed the Wire Pilot in a Weld Controller with the imbedded VME bus controller.

Source record↗
NASA NTRS1990

Custom electronic subsystems for the laboratory telerobotic manipulator

The National Aeronautics and Space Administration (NASA) Space Station Program presents new opportunities for the application of telerobotic and robotic systems. The Laboratory Telerobotic Manipulator (LTM) is a highly advanced 7 degrees-of-freedom (DOF) telerobotic/robotic manipulator. It was developed and built for the Automation Technology Branch at NASA's Langley Research Center (LaRC) for work in research and to demonstrate ground-based telerobotic manipulator system hardware and software systems for future NASA applications in the hazardous environment of space. The LTM manipulator uses an embedded wiring design with all electronics, motor power, and control and communication cables passing through the pitch-yaw differential joints. This design requires the number of cables passing through the pitch/yaw joint to be kept to a minimum. To eliminate the cables needed to carry each pitch-yaw joint's sensor data to the VME control computers, a custom-embedded electronics package for each manipulator joint was developed. The electronics package collects and sends the joint's sensor data to the VME control computers over a fiber optic cable. The electronics package consist of five individual subsystems: the VME Link Processor, the Joint Processor and the Joint Processor power supply in the joint module, the fiber optics communications system, and the electronics and motor power cabling.

Glassell, R. L.↗
NASA NTRS2001

Lessons Learned Using COTS Electronics for the International Space Station Radiation Environment

The mantra of 'Faster, Better, Cheaper' has to a large degree been interpreted as using Commercial Off-the-Shelf (COTS) components and/or circuit boards. One of the first space applications to actually use COTS in space along with radiation performance requirements was the Expedite the Processing of Experiments to Space Station (EXPRESS) Rack program, for the International Space Station (ISS). In order to meet the performance, cost and schedule targets, military grade Versa Module Eurocard (VME) was selected as the baseline design for the main computer, the Rack Interface Controller (RIC). VME was chosen as the computer backplane because of the large variety of military grade boards available, which were designed to meet the military environmental specifications (thermal, shock, vibration, etc.). These boards also have a paper pedigree in regards to components. Since these boards exceeded most ISS environmental requirements, it was reasoned using COTS mid-grade VME boards, as opposed to designing custom boards could save significant time and money. It was recognized up front the radiation environment of ISS, while benign compared to many space flight applications, would be the main challenge to using COTS. Thus in addition to selecting vendors on how well their boards met the usual performance and environmental specifications, the board's parts lists were reviewed on how well they would perform in the ISS radiation environment. However, issues with verifying that the available radiation test data was applicable to the actual part used, vendor part design changes and the fact most parts did not have valid test data soon complicated board and part selection in regards to radiation.

Blumer, John H.↗
NASA NTRS2003

Signal-Conditioning Amplifier Recorders

Signal-conditioning amplifier recorders (SCAmpRs) have been proposed as a means of simplifying and upgrading the Kennedy Space Center (KSC) Ground Measurement System (GMS), which is a versatile data-acquisition system that gathers and records a variety of measurement data before and during the launch of a space shuttle. In the present version of the GMS system, signal conditioning amplifiers digitize and transmit data to a VME chassis that multiplexes up to 416 channels. The data is transmitted via a high-speed data bus to a second VME chassis where it is available for snapshots. The data is passed from the second VME chassis to a high-speed data recorder. This process is duplicated for installations at two launch pads and the Vehicle Assembly Building (VAB). Since any failure of equipment in the data path results in loss of data, much of the system is redundant. The architecture of the existing GMS limits expansion or any modification to the system to meet changing requirements because of the cost and time required. A SCAmpR-based system is much more flexible. The basis of the simplification, flexibility, and reliability is the shifting of the recording function to the individual amplifier channels. Each SCAmpR is a self-contained single channel data acquisition system, which in its current implementation, has a data storage capacity of up to 30 minutes when operating at the fastest data sampling rates. The SCAmpR channels are self-configuring and self-calibrating. Multiple SCAmpR channels are ganged on printed circuit boards and mounted in a chassis that provides power, a network hub, and Inter-Range Instrument Group (IRIG) time signals. The SCAmpR channels share nothing except physical mounting on a circuit board. All circuitry is electrically separate for each channel. All that is necessary to complete the data acquisition system is a single master computer tied to the SCAmpR channels by standard network equipment. The size of the data acquisition system dictates the requirements for the specific network equipment.

Medelius, Pedro J.↗
NASA NTRS2003

A Timer for Synchronous Digital Systems

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

McKenney, Elizabeth↗
NASA NTRS1989

Conference on Real-Time Computer Applications in Nuclear, Particle and Plasma Physics, 6th, Williamsburg, VA, May 15-19, 1989, Proceedings

Papers on real-time computer applications in nuclear, particle, and plasma physics are presented, covering topics such as expert systems tactics in testing FASTBUS segment interconnect modules, trigger control in a high energy physcis experiment, the FASTBUS read-out system for the Aleph time projection chamber, a multiprocessor data acquisition systems, DAQ software architecture for Aleph, a VME multiprocessor system for plasma control at the JT-60 upgrade, and a multiasking, multisinked, multiprocessor data acquisition front end. Other topics include real-time data reduction using a microVAX processor, a transputer based coprocessor for VEDAS, simulation of a macropipelined multi-CPU event processor for use in FASTBUS, a distributed VME control system for the LISA superconducting Linac, a distributed system for laboratory process automation, and a distributed system for laboratory process automation. Additional topics include a structure macro assembler for the event handler, a data acquisition and control system for Thomson scattering on ATF, remote procedure execution software for distributed systems, and a PC-based graphic display real-time particle beam uniformity.

Pordes, Ruth↗
NASA NTRS2001

Flight Computer Processing Avionics for Space Station Microgravity Experiments: A Risk Assessment of Commercial Off-the-Shelf Utilization

NASA/Marshall Space Flight Center (MSFC) is continually looking for ways to reduce the costs and schedule and minimize the technical risks during the development of microgravity programs. One of the more prominent ways to minimize the cost and schedule is to use off-the-shelf hardware (OTS). However, the use of OTS often increases the risk. This paper addresses relevant factors considered during the selection and utilization of commercial off-the-shelf (COTS) flight computer processing equipment for the control of space station microgravity experiments. The paper will also discuss how to minimize the technical risks when using COTS processing hardware. Two microgravity experiments for which the COTS processing equipment is being evaluated for are the Equiaxed Dendritic Solidification Experiment (EDSE) and the Self-diffusion in Liquid Elements (SDLE) experiment. Since MSFC is the lead center for Microgravity research, EDSE and SDLE processor selection will be closely watched by other experiments that are being designed to meet payload carrier requirements. This includes the payload carriers planned for the International Space Station (ISS). The purpose of EDSE is to continue to investigate microstructural evolution of, and thermal interactions between multiple dendrites growing under diffusion controlled conditions. The purpose of SDLE is to determine accurate self-diffusivity data as a function of temperature for liquid elements selected as representative of class-like structures. In 1999 MSFC initiated a Center Director's Discretionary Fund (CDDF) effort to investigate and determine the optimal commercial data bus architecture that could lead to faster, better, and lower cost data acquisition systems for the control of microgravity experiments. As part of this effort various commercial data acquisition systems were acquired and evaluated. This included equipment with various form factors, (3U, 6U, others) and equipment that utilized various bus structures, (VME, PC104, STD bus). This evaluation of hardware was performed in conjunction with a trade study that considered over twenty (20) different factors relevant to the selection of an optimum design approach. These factors included; safety, sizing and timing, radiation hardness and single event upset, power consumption, heat dissipation, size and volume, expected service life, maintainability, heritage, operating systems, requirements for software reuse, availability of compatible interface boards, relative cost, schedule, reliability, EMI/EMC factors, "hot swap" capability, standards for conduction cooling, I/O capabilities, unique carrier requirements and operating system considerations. The approach to evaluate Safety as part of this study included a review of the Preliminary Hazard Analysis (PHA) for each of the experiment designs and a determination of how each hazard could be addressed and eliminated when different processors were selected. This included evaluating various design approaches and trade-offs between fault tolerant designs and fail-safe designs in accordance with NSTS 1700.7B. This will include the results of radiation testing where available. Various operating systems, such as VxWorks, Linux, QNX, and Embedded NT are evaluated and the advantages and disadvantages of their utilization are also addressed. Design implementation strategies for the various operating systems are considered and discussed. This paper presents the results and recommendations from this trade study. Preliminary conclusions from this study are that safety concerns from lack or radiation testing on COTS equipment can be addressed by additional testing and design considerations, the PC104 bus provided adequate I/O for the SDLE and EDSE microgravity experiments, and PC104 bus components offered significant advantages over VME and cPCI for weight and space reductions.

Estes, Howard↗
NASA NTRS2001

Determination of an Optimal Commercial Data Bus Architecture for a Flight Data System

NASA/Marshall Space Flight Center (MSFC) is continually looking for methods to reduce cost and schedule while keeping the quality of work high. MSFC is NASA's lead center for space transportation and microgravity research. When supporting NASA's programs several decisions concerning the avionics system must be made. Usually many trade studies must be conducted to determine the best ways to meet the customer's requirements. When deciding the flight data system, one of the first trade studies normally conducted is the determination of the data bus architecture. The schedule, cost, reliability, and environments are some of the factors that are reviewed in the determination of the data bus architecture. Based on the studies, the data bus architecture could result in a proprietary data bus or a commercial data bus. The cost factor usually removes the proprietary data bus from consideration. The commercial data bus's range from Versa Module Eurocard (VME) to Compact PCI to STD 32 to PC 104. If cost, schedule and size are prime factors, VME is usually not considered. If the prime factors are cost, schedule, and size then Compact PCI, STD 32 and PC104 are the choices for the data bus architecture. MSFC's center director has funded a study from his discretionary fund to determine an optimal low cost commercial data bus architecture. The goal of the study is to functionally and environmentally test Compact PCI, STD 32 and PC 104 data bus architectures. This paper will summarize the results of the data bus architecture study.

Crawford, Kevin↗
NASA NTRS1987

System architecture of a gallium arsenide one-gigahertz digital IC tester

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Fouts, Douglas J.↗
NASA NTRS1990

Beam rider for an Articulated Robot Manipulator (ARM) accurate positioning of long flexible manipulators

Laser beam positioning and beam rider modules were incorporated into the long hollow flexible segment of an articulated robot manipulator (ARM). Using a single laser beam, the system determined the position of the distal ARM endtip, with millimetric precision, in six degrees of freedom, at distances of up to 10 meters. Preliminary designs, using space rated technology for the critical systems, of a two segmented physical ARM, with a single and a dual degree of freedom articulation, were developed, prototyped, and tested. To control the positioning of the physical ARM, an indirect adaptive controller, which used the mismatch between the position of the laser beam under static and dynamic conditions, was devised. To predict the behavior of the system and test the concept, a computer simulation model was constructed. A hierarchical artificially intelligent real time ADA operating system program structure was created. The software was designed for implementation on a dedicated VME bus based Intel 80386 administered parallel processing multi-tasking computer system.

Malachowski, M. J.↗
NASA NTRS1989

Implementation and design of a teleoperation system based on a VMEBUS/68020 pipelined architecture

A pipelined control design and architecture for a force-feedback teleoperation system that is being implemented at the Jet Propulsion Laboratory and which will be integrated with the autonomous portion of the testbed to achieve share control is described. At the local site, the operator sees real-time force/torque displays and moves two 6-degree of freedom (dof) force-reflecting hand-controllers as his hands feel the contact force/torques generated at the remote site where the robots interact with the environment. He also uses a graphical user menu to monitor robot states and specify system options. The teleoperation software is written in the C language and runs on MC68020-based processor boards in the VME chassis, which utilizes a real-time operating system; the hardware is configured to realize a four-stage pipeline configuration. The environment is very flexible, such that the system can easily be configured as a stand-alone facility for performing independent research in human factors, force control, and time-delayed systems.

Lee, Thomas S.↗
NASA NTRS1989

Robotic control of the seven-degree-of-freedom NASA laboratory telerobotic manipulator

A computationally efficient robotic control scheme for the NASA Laboratory Telerobotic Manipulator (LTM) is presented. This scheme utilizes the redundancy of the seven-degree-of-freedom LTM to avoid joint limits and singularities. An analysis to determine singular configurations is presented. Performance criteria are determined based on the joint limits and singularity analysis. The control scheme is developed in the framework of resolved rate control using the gradient projection method, and it does not require the generalized inverse of the Jacobian. An efficient formulation for determining the joint velocities of the LTM is obtained. This control scheme is well suited for real-time implementation, which is essential if the end-effector trajectory is continuously modified based on sensory feedback. Implementation of this scheme on a Motorola 68020 VME bus-based controller of the LTM is in progress. Simulation results demonstrating the redundancy utilization in the robotic mode are presented.

Dubey, R. V.↗
NASA NTRS1990

Health monitoring system for the SSME - Hardware architecture study

This paper presents a hardware architecture for a health monitoring system (HMS) for the SSME. The architecture study was conducted in conjunction with a NASA sponsored program to develop a framework for SSME HMS for (1) ground test and, potentially (2) flight applications. The requirements for both systems are both stated and analyzed. A multiprocessor distributed VME system is envisioned for the ground-test hardware. By repackaging the boards, the same concept is shown to be usable for the flight system. The paper concludes with an analysis of weight, power, and reliability with respect to variations in functionality.

Kamenetz, Jeffry K.↗
NASA NTRS1990

Performance measurements of the first RAID prototype

The performance is examined of Redundant Arrays of Inexpensive Disks (RAID) the First, a prototype disk array. A hierarchy of bottlenecks was discovered in the system that limit overall performance. The most serious is the memory system contention on the Sun 4/280 host CPU, which limits array bandwidth to 2.3 MBytes/sec. The array performs more successfully on small random operations, achieving nearly 300 I/Os per second before the Sun 4/280 becomes CPU limited. Other bottlenecks in the system are the VME backplane, bandwidth on the disk controller, and overheads associated with the SCSI protocol. All are examined in detail. The main conclusion is that to achieve the potential bandwidth of arrays, more powerful CPU's alone will not suffice. Just as important are adequate host memory bandwidth and support for high bandwidth on disk controllers. Current disk controllers are more often designed to achieve large numbers of small random operations, rather than high bandwidth. Operating systems also need to change to support high bandwidth from disk arrays. In particular, they should transfer data in larger blocks, and should support asynchronous I/O to improve sequential write performance.

Chervenak, Ann L.↗
NASA NTRS1991

NASA/Ames Research Center DC-8 data system

In-flight facility data acquisition, distribution, and recording on the NASA Ames Research Center (ARC) DC-8 are performed by the Data Acquisition and Distribution System (DADS). Navigational and environmental data collected by the DADS are converted to engineering units and distributed real-time to investigator stations once per second. Selected engineering units data are printed and displayed on closed circuit television monitors throughout flights. An in-flight graphical display of the DC-8 flight track (with barbs indicating wind direction and magnitude) has recently been added to the DADS capabilities. Logging of data run starts/stops and commentary from the mission director are also provided. All data are recorded to hard disk in-flight and archived to tape medium post-flight. Post-flight, hard copies of the track map and mission director's log are created by the DADS. The DADS is a distributed system consisting of a data subsystem, an Avionic Serial Data-to-VMEbus (ASD2VME) subsystem, and a host subsystem. Each subsystem has a dedicated central processing unit (CPU) and is capable of stand-alone operation. All three subsystems are housed in a single 20-slot VME chassis and communicate with each other over the VMEbus. The data and host subsystems are briefly discussed, and the DC-8 DADS internal configuration and system block diagram are presented.

Cherniss, S. C.↗
NASA NTRS1990

Implementing real-time robotic systems using CHIMERA II

A description is given of the CHIMERA II programming environment and operating system, which was developed for implementing real-time robotic systems. Sensor-based robotic systems contain both general- and special-purpose hardware, and thus the development of applications tends to be a time-consuming task. The CHIMERA II environment is designed to reduce the development time by providing a convenient software interface between the hardware and the user. CHIMERA II supports flexible hardware configurations which are based on one or more VME-backplanes. All communication across multiple processors is transparent to the user through an extensive set of interprocessor communication primitives. CHIMERA II also provides a high-performance real-time kernel which supports both deadline and highest-priority-first scheduling. The flexibility of CHIMERA II allows hierarchical models for robot control, such as NASREM, to be implemented with minimal programming time and effort.

Stewart, David B.↗