Introduction to Electronics, DAQ, Trigger (4/5)
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Soft Real-Time PID Control on a VME Computer
microPID (uPID) is a computer program for real-time proportional + integral + derivative (PID) control of a translation stage in a Fourier-transform ultraviolet spectrometer. microPID implements a PID control loop over a position profile at sampling rate of 8 kHz (sampling period 125microseconds). The software runs in a strippeddown Linux operating system on a VersaModule Eurocard (VME) computer operating in real-time priority queue using an embedded controller, a 16-bit digital-to-analog converter (D/A) board, and a laser-positioning board (LPB). microPID consists of three main parts: (1) VME device-driver routines, (2) software that administers a custom protocol for serial communication with a control computer, and (3) a loop section that obtains the current position from an LPB-driver routine, calculates the ideal position from the profile, and calculates a new voltage command by use of an embedded PID routine all within each sampling period. The voltage command is sent to the D/A board to control the stage. microPID uses special kernel headers to obtain microsecond timing resolution. Inasmuch as microPID implements a single-threaded process and all other processes are disabled, the Linux operating system acts as a soft real-time system.
Karayan, Vahag↗
Performance of a disk array prototype
A prototype disk array's component-performance limits are examined using SCSI bus traces, Sprite operating system traces, and user programs. The array performs successfully for a workload of small, random I/O operations, achieving 275 I/Os per second on 14 disks before the Sun4/280 host becomes CPU-limited. The prototype is less successful in delivering high throughput for large, sequential operations. Memory system contention on the Sun4/280 host limits throughput to 2.3 MBytes/sec under the Sprite Operating System. Throughput is also limited by the bandwidth supported by the VME backplane, disk controller and disks, and overheads associated with the SCSI protocol. We conclude that merely using a powerful host CPU and many disks will not provide the full bandwidth possible from disk arrays. Host memory bandwidth and throughput of disk controllers are equally important. In addition, operating systems should avoid unnecessary copy and cache flush operations that can saturate the host memory system.
Chervenak, Ann L.↗
Performance measurements of the first RAID prototype
The performance is examined of Redundant Arrays of Inexpensive Disks (RAID) the First, a prototype disk array. A hierarchy of bottlenecks was discovered in the system that limit overall performance. The most serious is the memory system contention on the Sun 4/280 host CPU, which limits array bandwidth to 2.3 MBytes/sec. The array performs more successfully on small random operations, achieving nearly 300 I/Os per second before the Sun 4/280 becomes CPU limited. Other bottlenecks in the system are the VME backplane, bandwidth on the disk controller, and overheads associated with the SCSI protocol. All are examined in detail. The main conclusion is that to achieve the potential bandwidth of arrays, more powerful CPU's alone will not suffice. Just as important are adequate host memory bandwidth and support for high bandwidth on disk controllers. Current disk controllers are more often designed to achieve large numbers of small random operations, rather than high bandwidth. Operating systems also need to change to support high bandwidth from disk arrays. In particular, they should transfer data in larger blocks, and should support asynchronous I/O to improve sequential write performance.
Chervenak, Ann L.↗
Redis-Based Streaming Architecture for Accelerator Beam Instrumentation DAQ Systems
The Fermilab Acceleraor Division, Beam Instrumentation Department, is always adopting modern and current software methodologies for complex DAQ architectures. This paper highlights the Redis Adapter (RA) as the key software component enabling high performance, modular communication between digitizers and distributed control systems by leveraging Redis and containerization. The RA provides a unified, efficient interface between Redis based data streams and consumer systems. In the legacy architecture, digitized data flowed through the custom, UDP based Distributed Data Communication Protocol in the middle layer. In the current system, DDCP remains the ingestion path, while the RA serves as the decoupling layer. The proposed system replaces old VME digitizers with a SOM-based digitizer that communicates with Redis using the RA. The RA acts as both a performance-critical bridge and a protocol-agnostic adapter, ensuring compatibility with legacy control frameworks while enabling future scalability and modularity. This restructuring of the middle layer also helps the system achieve high throughput, reduce latency, and simplify the data path. Finally, we will demonstrate how RA is utilized in our two core products to deliver both legacy compatibility and future flexibility.
Joshi, S. [Fermilab]↗
A Modern Ethernet Data Acquisition Architecture for Fermilab Beam Instrumentation
The Fermilab Accelerator Division, Instrumentation Department is adopting an open-source framework to replace our embedded VME-based data acquisition systems. Utilizing an iterative methodology, we first moved to embedded Linux, removing the need for VxWorks. Next, we adopted Ethernet on each data acquisition module eliminating the need for the VME backplane in addition to communicating with a rack mount server. Development of DDCP (Distributed Data Communications Protocol), allowed for an abstraction between the firmware and software layers. Each data acquisition module was adapted to read out using 1 GbE and aggregated at a switch which up linked to a 10 GbE network. Current development includes scaling the system to aggregate more modules, to increase bandwidth to support multiple systems and to adopt MicroTCA as a crate technology. The architecture was utilized on various beamlines around the Fermilab complex including PIP2IT, FAST/IOTA and the Muon Delivery Ring. In summary, we were able to develop a data acquisition framework which incrementally replaces VxWorks & VME hardware as well as increases our total bandwidth to 10 Gbit/s using off the shelf Ethernet technology.
43 PARTICLE ACCELERATORS↗
New Insertion Device Control System for the APS Upgrade
New Hybrid Permanent Magnet Undulators (HPMUs) have been designed and manufactured using servo motors for precise and reliable gap motion control for the Advanced Photon Source Upgrade (APS-U) project. Meanwhile, existing HPMUs equipped with legacy stepper motors are systematically replaced with servo motors. In parallel with mechanical modifications of the undulators, a comprehensive upgrade has been implemented for the control of the devices. This upgrade includes integration of standardized industrial components for replacement of motor controllers and motor drives using the Kollmorgen Programmable Controller Multi-axis Master (PCMM) controllers and the AKD2G series servo drives. Soft Input Output Controllers (IOCs) are developed and deployed to replace the legacy VME-based IOCs for both single-period undulators and Revolver undulators. In this paper, we will present the architecture of the new insertion device control system, including control mechanisms, interlock protocols, and tools for diagnostics and troubleshooting.
Li, W.↗
Design of a Channel Error Simulator using Virtual Instrument Techniques for the Initial Testing of TCP/IP and SCPS Protocols
There exists a need for designers and developers to have a method to conveniently test a variety of communications parameters for an overall system design. This is no different when testing network protocols as when testing modulation formats. In this report, we discuss a means of providing a networking test device specifically designed to be used for space communications. This test device is a PC-based Virtual Instrument (VI) programmed using the LabVIEW(TM) version 5 software suite developed by National Instruments(TM)TM. This instrument was designed to be portable and usable by others without special, additional equipment. The programming was designed to replicate a VME-based hardware module developed earlier at New Mexico State University (NMSU) and to provide expanded capabilities exceeding the baseline configuration existing in that module. This report describes the design goals for the VI module in the next section and follows that with a description of the design of the VI instrument. This is followed with a description of the validation tests run on the VI. An application of the error-generating VI to networking protocols is then given.
Horan, Stephen↗
Data Relay Board with Protocol for High-Speed, Free-Space Optical Communications
In a free-space optical communication system, the mitigation of transient outages through the incorporation of error-control methods is of particular concern, the outages being caused by scintillation fades and obscurants. The focus of this innovative technology is the development of a data relay system for a reliable high-data-rate free-spacebased optical-transport network. The data relay boards will establish the link, maintain synchronous connection, group the data into frames, and provide for automatic retransmission (ARQ) of lost or erred frames. A certain Quality of Service (QoS) can then be ensured, compatible with the required data rate. The protocol to be used by the data relay system is based on the draft CCSDS standard data-link protocol Proximity-1, selected by orbiters to multiple lander assets in the Mars network, for example. In addition to providing data-link protocol capabilities for the free-space optical link and buffering the data, the data relay system will interface directly with user applications over Gigabit Ethernet and/or with highspeed storage resources via Fibre Channel. The hardware implementation is built on a network-processor-based architecture. This technology combines the power of a hardware switch capable of data switching and packet routing at Gbps rates, with the flexibility of a software- driven processor that can host highly adaptive and reconfigurable protocols used, for example, in wireless local-area networks (LANs). The system will be implemented in a modular multi-board fashion. The main hardware elements of the data relay system are the new data relay board developed by Rockwell Scientific, a COTS Gigabit Ethernet board for user interface, and a COTS Fibre Channel board that connects to local storage. The boards reside in a cPCI back plane, and can be housed in a VME-type enclosure.
Wright, Malcolm↗
Reusable Rack Interface Controller Common Software for Various Science Research Racks on the International Space Station
The purpose of the EXPRESS (Expedite the PRocessing of Experiments to Space Station) rack project is to provide a set of predefined interfaces for scientific payloads which allow rapid integration into a payload rack on International Space Station (ISS). VxWorks' was selected as the operating system for the rack and payload resource controller, primarily based on the proliferation of VME (Versa Module Eurocard) products. These products provide needed flexibility for future hardware upgrades to meet everchanging science research rack configuration requirements. On the International Space Station, there are multiple science research rack configurations, including: 1) Human Research Facility (HRF); 2) EXPRESS ARIS (Active Rack Isolation System); 3) WORF (Window Observational Research Facility); and 4) HHR (Habitat Holding Rack). The RIC (Rack Interface Controller) connects payloads to the ISS bus architecture for data transfer between the payload and ground control. The RIC is a general purpose embedded computer which supports multiple communication protocols, including fiber optic communication buses, Ethernet buses, EIA-422, Mil-Std-1553 buses, SMPTE (Society Motion Picture Television Engineers)-170M video, and audio interfaces to payloads and the ISS. As a cost saving and software reliability strategy, the Boeing Payload Software Organization developed reusable common software where appropriate. These reusable modules included a set of low-level driver software interfaces to 1553B. RS232, RS422, Ethernet buses, HRDL (High Rate Data Link), video switch functionality, telemetry processing, and executive software hosted on the FUC computer. These drivers formed the basis for software development of the HRF, EXPRESS, EXPRESS ARIS, WORF, and HHR RIC executable modules. The reusable RIC common software has provided extensive benefits, including: 1) Significant reduction in development flow time; 2) Minimal rework and maintenance; 3) Improved reliability; and 4) Overall reduction in software life cycle cost. Due to the limited number of crew hours available on ISS for science research, operational efficiency is a critical customer concern. The current method of upgrading RIC software is a time consuming process; thus, an improved methodology for uploading RIC software is currently under evaluation.
Lu, George C.↗