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This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and at a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.
This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.