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Development of Stochastic Voronoi Lattice Structures via Two-Photon Polymerization

Low-density polymer foams of varying sizes, shapes, and densities are of specific interest to the inertial confinement fusion (ICF) program and related high-energy density plasma physics research. Historically, these foams are comprised of polystyrene or other low atomic number materials and have densities in the 30 to 300 mg/cm 3 range. However, at the lower end of this density range, these traditional polymer foams become fragile and difficult to cast and machine into the geometries needed. Recently, the need by experimentalists for materials with densities below 30 mg/cm 3 has increased. To address these needs, we are developing three-dimensional (3-D) printing techniques to create high-precision, low-density, and repeatable complex lattice structures. Using two-photon polymerization 3-D printing, we recently developed the first 5 mg/cm3 low-density lattice structure having an annular hemispherical shape. These microscale to mesoscale structures were modeled and designed using the nTopology software, specifically utilizing the "Voronoi volume lattice" and "random points in body" option blocks. All printing operations were performed using the Nanoscribe Photonic Professional GT instrument. Characterization of these 3-D structures was conducted using various microscopic and X-ray tomographic imaging techniques. Furthermore, overall printed part sizes ranged from 1 to 5 mm in diameter and were composed of lattice ligaments having thicknesses in the 3- to 5-µm range. These structures have been incorporated into ICF targets recently shot on both the University of Rochester’s Laboratory of Laser Energetics Omega laser and the National Ignition Facility.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Interference Lattice-based Loop Nest Tilings for Stencil Computations

A common method for improving performance of stencil operations on structured multi-dimensional discretization grids is loop tiling. Tile shapes and sizes are usually determined heuristically, based on the size of the primary data cache. We provide a lower bound on the numbers of cache misses that must be incurred by any tiling, and a close achievable bound using a particular tiling based on the grid interference lattice. The latter tiling is used to derive highly efficient loop orderings. The total number of cache misses of a code is the sum of (necessary) cold misses and misses caused by elements being dropped from the cache between successive loads (replacement misses). Maximizing temporal locality is equivalent to minimizing replacement misses. Temporal locality of loop nests implementing stencil operations is optimized by tilings that avoid data conflicts. We divide the loop nest iteration space into conflict-free tiles, derived from the cache miss equation. The tiling involves the definition of the grid interference lattice an equivalence class of grid points whose images in main memory map to the same location in the cache-and the construction of a special basis for the lattice. Conflicts only occur on the boundaries of the tiles, unless the tiles are too thin. We show that the surface area of the tiles is bounded for grids of any dimensionality, and for caches of any associativity, provided the eccentricity of the fundamental parallelepiped (the tile spanned by the basis) of the lattice is bounded. Eccentricity is determined by two factors, aspect ratio and skewness. The aspect ratio of the parallelepiped can be bounded by appropriate array padding. The skewness can be bounded by the choice of a proper basis. Combining these two strategies ensures that pathologically thin tiles are avoided. They do not, however, minimize replacement misses per se. The reason is that tile visitation order influences the number of data conflicts on the tile boundaries. If two adjacent tiles are visited successively, there will be no replacement misses on the shared boundary. The iteration space may be covered with pencils larger than the size of the cache while avoiding data conflicts if the pencils are traversed by a scanning-face method. Replacement misses are incurred only on the boundaries of the pencils, and the number of misses is minimized by maximizing the volume of the scanning face, not the volume of the tile. We present an algorithm for constructing the most efficient scanning face for a given grid and stencil operator. In two dimensions it is based on a continued fraction algorithm. In three dimensions it follows Voronoi's successive minima algorithm. We show experimental results of using the scanning face, and compare with canonical loop orderings.

VanderWijngaart, Rob F.↗