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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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16 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy↗
NASA NTRS2010

Fabrication of Single, Vertically Aligned Carbon Nanotubes in 3D Nanoscale Architectures

Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are structurally and chemically compatible with the high-temperature synthesis of the PECVD-grown tubes. The techniques offer a wafer-scale process solution for integrating single PECVD-grown nanotubes into novel architectures that should accelerate their integration in 3D electronics in general. NASA can directly benefit from this technology for its extreme-environment planetary missions. Current Si transistors are inherently more susceptible to high radiation, and do not tolerate extremes in temperature. These novel 3D nanoscale architectures can form the basis for NEMS switches that are inherently less susceptible to radiation or to thermal extremes.

Kaul, Anupama B.↗
NASA NTRS1991

A grid amplifier

A 50-MESFET grid amplifier is reported that has a gain of 11 dB at 3.3 GHz. The grid isolates the input from the output by using vertical polarization for the input beam and horizontal polarization for the transmitted output beam. The grid unit cell is a two-MESFET differential amplifier. A simple calibration procedure allows the gain to be calculated from a relative power measurement. This grid is a hybrid circuit, but the structure is suitable for fabrication as a monolithic wafer-scale integrated circuit, particularly at millimeter wavelengths.

Kim, Moonil↗
NASA NTRS1992

A new fabrication technique for back-to-back varactor diodes

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

Smith, R. Peter↗
NASA NTRS2004

Plasma Enhanced Growth of Carbon Nanotubes For Ultrasensitive Biosensors

The multitude of considerations facing nanostructure growth and integration lends itself to combinatorial optimization approaches. Rapid optimization becomes even more important with wafer-scale growth and integration processes. Here we discuss methodology for developing plasma enhanced CVD growth techniques for achieving individual, vertically aligned carbon nanostructures that show excellent properties as ultrasensitive electrodes for nucleic acid detection. We utilize high throughput strategies for optimizing the upstream and downstream processing and integration of carbon nanotube electrodes as functional elements in various device types. An overview of ultrasensitive carbon nanotube based sensor arrays for electrochemical bio-sensing applications and the high throughput methodology utilized to combine novel electrode technology with conventional MEMS processing will be presented.

Cassell, Alan M.↗
NASA NTRS2004

Plasma Enhanced Growth of Carbon Nanotubes For Ultrasensitive Biosensors

The multitude of considerations facing nanostructure growth and integration lends itself to combinatorial optimization approaches. Rapid optimization becomes even more important with wafer-scale growth and integration processes. Here we discuss methodology for developing plasma enhanced CVD growth techniques for achieving individual, vertically aligned carbon nanostructures that show excellent properties as ultrasensitive electrodes for nucleic acid detection. We utilize high throughput strategies for optimizing the upstream and downstream processing and integration of carbon nanotube electrodes as functional elements in various device types. An overview of ultrasensitive carbon nanotube based sensor arrays for electrochemical biosensing applications and the high throughput methodology utilized to combine novel electrode technology with conventional MEMS processing will be presented.

Cassell, Alan M.↗
NASA NTRS2004

Integrating Carbon Nanotubes For Atomic Force Microscopy Imaging Applications

Carbon nanotube (CNT) related nanostructures possess remarkable electrical, mechanical, and thermal properties. To produce these nanostructures for real world applications, a large-scale controlled growth of carbon nanotubes is crucial for the integration and fabrication of nanodevices and nanosensors. We have taken the approach of integrating nanopatterning and nanomaterials synthesis with traditional silicon micro fabrication techniques. This integration requires a catalyst or nanomaterial protection scheme. In this paper, we report our recent work on fabricating wafer-scale carbon nanotube AFM cantilever probe tips. We will address the design and fabrication considerations in detail, and present the preliminary scanning probe test results. This work may serve as an example of rational design, fabrication, and integration of nanomaterials for advanced nanodevice and nanosensor applications.

Ye, Qi↗
NASA NTRS2009

NASA Tech Briefs, September 2009

opics covered include: Filtering Water by Use of Ultrasonically Vibrated Nanotubes; Computer Code for Nanostructure Simulation; Functionalizing CNTs for Making Epoxy/CNT Composites; Improvements in Production of Single-Walled Carbon Nanotubes; Progress Toward Sequestering Carbon Nanotubes in PmPV; Two-Stage Variable Sample-Rate Conversion System; Estimating Transmitted-Signal Phase Variations for Uplink Array Antennas; Board Saver for Use with Developmental FPGAs; Circuit for Driving Piezoelectric Transducers; Digital Synchronizer without Metastability; Compact, Low-Overhead, MIL-STD-1553B Controller; Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM; Differential InP HEMT MMIC Amplifiers Embedded in Waveguides; Improved Aerogel Vacuum Thermal Insulation; Fluoroester Co-Solvents for Low-Temperature Li+ Cells; Using Volcanic Ash to Remove Dissolved Uranium and Lead; High-Efficiency Artificial Photosynthesis Using a Novel Alkaline Membrane Cell; Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays; Micro-Horn Arrays for Ultrasonic Impedance Matching; Improved Controller for a Three-Axis Piezoelectric Stage; Nano-Pervaporation Membrane with Heat Exchanger Generates Medical-Grade Water; Micro-Organ Devices; Nonlinear Thermal Compensators for WGM Resonators; Dynamic Self-Locking of an OEO Containing a VCSEL; Internal Water Vapor Photoacoustic Calibration; Mid-Infrared Reflectance Imaging of Thermal-Barrier Coatings; Improving the Visible and Infrared Contrast Ratio of Microshutter Arrays; Improved Scanners for Microscopic Hyperspectral Imaging; Rate-Compatible LDPC Codes with Linear Minimum Distance; PrimeSupplier Cross-Program Impact Analysis and Supplier Stability Indicator Simulation Model; Integrated Planning for Telepresence With Time Delays; Minimizing Input-to-Output Latency in Virtual Environment; Battery Cell Voltage Sensing and Balancing Using Addressable Transformers; Gaussian and Lognormal Models of Hurricane Gust Factors; Simulation of Attitude and Trajectory Dynamics and Control of Multiple Spacecraft; Integrated Modeling of Spacecraft Touch-and-Go Sampling; Spacecraft Station-Keeping Trajectory and Mission Design Tools; Efficient Model-Based Diagnosis Engine; and DSN Simulator.

Source record↗
NASA NTRS2007

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata↗
NASA NTRS2013

Planar Superconducting Millimeter-Wave/Terahertz Channelizing Filter

This innovation is a compact, superconducting, channelizing bandpass filter on a single-crystal (0.45 m thick) silicon substrate, which operates from 300 to 600 GHz. This device consists of four channels with center frequencies of 310, 380, 460, and 550 GHz, with approximately 50-GHz bandwidth per channel. The filter concept is inspired by the mammalian cochlea, which is a channelizing filter that covers three decades of bandwidth and 3,000 channels in a very small physical space. By using a simplified physical cochlear model, and its electrical analog of a channelizing filter covering multiple octaves bandwidth, a large number of output channels with high inter-channel isolation and high-order upper stopband response can be designed. A channelizing filter is a critical component used in spectrometer instruments that measure the intensity of light at various frequencies. This embodiment was designed for MicroSpec in order to increase the resolution of the instrument (with four channels, the resolution will be increased by a factor of four). MicroSpec is a revolutionary wafer-scale spectrometer that is intended for the SPICA (Space Infrared Telescope for Cosmology and Astrophysics) Mission. In addition to being a vital component of MicroSpec, the channelizing filter itself is a low-resolution spectrometer when integrated with only an antenna at its input, and a detector at each channel s output. During the design process for this filter, the available characteristic impedances, possible lumped element ranges, and fabrication tolerances were identified for design on a very thin silicon substrate. Iterations between full-wave and lumped-element circuit simulations were performed. Each channel s circuit was designed based on the availability of characteristic impedances and lumped element ranges. This design was based on a tabular type bandpass filter with no spurious harmonic response. Extensive electromagnetic modeling for each channel was performed. Four channels, with 50-GHz bandwidth, were designed, each using multiple transmission line media such as microstrip, coplanar waveguide, and quasi-lumped components on 0.45- m thick silicon. In the design process, modeling issues had to be overcome. Due to the extremely high frequencies, very thin Si substrate, and the superconducting metal layers, most commercially available software fails in various ways. These issues were mitigated by using alternative software that was capable of handling them at the expense of greater simulation time. The design of on-chip components for the filter characterization, such as a broadband antenna, Wilkinson power dividers, attenuators, detectors, and transitions has been completed.

Ehsan, Negar↗
NASA NTRS2011

High-Throughput Processes and Structural Characterization of Single-Nanotube Based Devices for 3D Electronics

We have developed manufacturable approaches to form single, vertically aligned carbon nanotubes, where the tubes are centered precisely, and placed within a few hundred nm of 1-1.5 micron deep trenches. These wafer-scale approaches were enabled by chemically amplified resists and inductively coupled Cryo-etchers to form the 3D nanoscale architectures. The tube growth was performed using dc plasmaenhanced chemical vapor deposition (PECVD), and the materials used for the pre-fabricated 3D architectures were chemically and structurally compatible with the high temperature (700 C) PECVD synthesis of our tubes, in an ammonia and acetylene ambient. The TEM analysis of our tubes revealed graphitic basal planes inclined to the central or fiber axis, with cone angles up to 30 deg. for the particular growth conditions used. In addition, bending tests performed using a custom nanoindentor, suggest that the tubes are well adhered to the Si substrate. Tube characteristics were also engineered to some extent, by adjusting growth parameters, such as Ni catalyst thickness, pressure and plasma power during growth.

top-down fabrication↗
NASA NTRS2009

High-Throughput Top-Down and Bottom-Up Processes for Forming Single-Nanotube Based Architectures for 3D Electronics

We have developed manufacturable approaches to form single, vertically aligned carbon nanotubes, where the tubes are centered precisely, and placed within a few hundred nm of 1-1.5 micron deep trenches. These wafer-scale approaches were enabled by chemically amplified resists and inductively coupled Cryo-etchers for forming the 3D nanoscale architectures. The tube growth was performed using dc plasma-enhanced chemical vapor deposition (PECVD), and the materials used for the pre-fabricated 3D architectures were chemically and structurally compatible with the high temperature (700 C) PECVD synthesis of our tubes, in an ammonia and acetylene ambient. Tube characteristics were also engineered to some extent, by adjusting growth parameters, such as Ni catalyst thickness, pressure and plasma power during growth. Such scalable, high throughput top-down fabrication techniques, combined with bottom-up tube synthesis, should accelerate the development of PECVD tubes for applications such as interconnects, nano-electromechanical (NEMS), sensors or 3D electronics in general.

plasma-enhanced chemical vapor deposition (PECVD),↗
NASA NTRS2016

Key Elements of a Low Voltage, Ultracompact Plasma Spectrometer

Taking advantage of technological developments in wafer-scale processing over the past two decades, such as deep etching, 3-D chip stacking, and double-sided lithography, we have designed and fabricated the key elements of an ultracompact 1.5cm (exp 3)plasma spectrometer that requires only low-voltage power supplies, has no microchannel plates, and has a high aperture area to instrument volume ratio. The initial design of the instrument targets the measurement of charged particles in the 3-20keV range with a highly directional field of view and a 100 duty cycle; i.e., the entire energy range Is continuously measured. In addition to reducing mass, size, and voltage requirements, the new design will affect the manufacturing process of plasma spectrometers, enabling large quantities of identical instruments to be manufactured at low individual unit cost. Such a plasma spectrometer is ideal for heliophysics plasma investigations, particularly for small satellite and multispacecraft missions. Two key elements of the instrument have been fabricated: the collimator and the energy analyzer. An initial collimator transparency of 20 with 3deg x 3deg angular resolution was achieved. The targeted 40 collimator transparency appears readily achievable. The targeted energy analyzer scaling factor of 1875 was achieved; i.e.20 keV electrons were selected for only a 10.7V bias voltage in the energy analyzer.

Scime, E. E.↗
NASA NTRS2016

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

We are exploring the properties of electron-beam evaporated molybdenum thin films on silicon nitride coated silicon wafers at substrate temperatures between room temperature and 650 C. The temperature dependence of film stress, transition temperature, and electrical properties are presented. X-ray diffraction measurements are performed to gain information on molybdenum crystallite size and growth. Results show the dominant influence of the crystallite size on the intrinsic properties of our films. Wafer-scale uniformity, wafer yield, and optimal thermal bias regime for TES fabrication are discussed.

Microcalorimeter↗