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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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15 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Securing 3D NAND Without Density Loss via In-Situ Encryption Using a Single Transistor XOR Cell

In this article, we push lightweight XOR-based in-situ encryption to extreme density by proposing a singletransistor XOR memory cell and applying it to 3D NAND, enabling secure data storage without density loss. Using a ferroelectric field-effect transistor (FeFET) as an example technology, we demonstrate that: i) a single-transistor memory can realize the XOR function by exploiting the ability to charge the source and drain separately and control current flow direction, eliminating the need for conventional encrypted cells that rely on complementary devices; ii) with a XOR-based cipher, encryption and decryption can be mapped to in-situ array operations, where ciphertext is stored as the threshold voltage (VTH) states of FeFETs in a NAND string, and decryption is achieved through read operations using key-dependent complementary source/drain bias; iii) the proposed technique is scalable to multi-level cell (MLC) storage by encrypting and decrypting data bit by bit; iv) using an integrated NAND FeFET array, we experimentally demonstrate encryption and decryption operations for both single-level cell (SLC) and MLC storage; v) systemlevel benchmarking shows that the proposed technique achieves 48× and 278× improvements in encryption and decryption throughput, respectively, compared to AES.

36 MATERIALS SCIENCE↗
NASA NTRS1996

RAID-S Technical Overview: Raid 4 and 5-Compliant Hardware and Software Functionality Improves Data Availability Through Use of XOR-Capable Disks in an Integrated Cached Disk Array

The purpose of this paper is to provide a technical description of redundant array of independent disks - Symmetrix (RAID-S). It is intended to give the reader an understanding of how RAID-S is architected and implemented in the EMC Symmetrix 3000/5000 series integrated cached disk array. Topics include RAID-S taxonomy, configuration considerations, operational characteristics, performance, and implementation guidelines.

Quinn, Brett↗
NASA NTRS1983

Implementing Exclusive-OR Logic

Two integrated circuits, BCD-to-decimal decoder and four-input NAND gate, form basic four, input XOR circuit. Multiple-input exclusive-OR logic is implemented by combining several basic elements. 16-input XOR gate is assembled from five NAND gates and five decoders. Same principle extended to handle more inputs.

Hough, M. E.↗
NASA NTRS2011

Kepler and Ground-Based Transits of the exo-Neptune HAT-P-11b

We analyze 26 archival Kepler transits of the exo-Neptune HAT-P-11b, supplemented by ground-based transits observed in the blue (B band) and near-IR (J band). Both the planet and host star are smaller than previously believed; our analysis yields Rp = 4.31 R xor 0.06 R xor and Rs = 0.683 R solar mass 0.009 R solar mass, both about 3 sigma smaller than the discovery values. Our ground-based transit data at wavelengths bracketing the Kepler bandpass serve to check the wavelength dependence of stellar limb darkening, and the J-band transit provides a precise and independent constraint on the transit duration. Both the limb darkening and transit duration from our ground-based data are consistent with the new Kepler values for the system parameters. Our smaller radius for the planet implies that its gaseous envelope can be less extensive than previously believed, being very similar to the H-He envelope of GJ 436b and Kepler-4b. HAT-P-11 is an active star, and signatures of star spot crossings are ubiquitous in the Kepler transit data. We develop and apply a methodology to correct the planetary radius for the presence of both crossed and uncrossed star spots. Star spot crossings are concentrated at phases 0.002 and +0.006. This is consistent with inferences from Rossiter-McLaughlin measurements that the planet transits nearly perpendicular to the stellar equator. We identify the dominant phases of star spot crossings with active latitudes on the star, and infer that the stellar rotational pole is inclined at about 12 deg 5 deg to the plane of the sky. We point out that precise transit measurements over long durations could in principle allow us to construct a stellar Butterfly diagram to probe the cyclic evolution of magnetic activity on this active K-dwarf star.

Deming, Drake↗
DOE OSTI2024

Encoding of symbols for a computer interconnect based on frequency of symbol values

Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

SeyedzadehDelcheh, SeyedMohammad↗
DOE OSTI2024

CMOS-Based Single-Cycle in-Memory XOR/XNOR

Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

High-speed tunable generation of random number distributions using actuated perpendicular magnetic tunnel junctions

Perpendicular magnetic tunnel junctions (pMTJs) actuated by nanosecond pulses are emerging as promising devices for true random number generation (TRNG) due to their intrinsic stochastic behavior and high throughput. In this work, we demonstrate the tunability and quality of random number distributions generated by pMTJs operating at a frequency of 104 MHz. First, changing the pulse amplitude is used to systematically vary the probability bias. The variance of the resulting bitstreams closely matches the expected binomial distribution, demonstrating consistency with an underlying sequence of Bernoulli trials. Second, the quality of uniform distributions of 8-bit random numbers generated with a probability bias of 0.5 is considered. A reduced chi-square analysis of these data shows that only two XOR operations are sufficient to achieve this distribution with p-values greater than 0.05. Finally, we show that there is a correlation between long-term probability bias variations and pMTJ resistance. These findings suggest that variations in the characteristics of the pMTJ underlie the observed variation of probability bias. In conclusion, our results highlight the potential of stochastically actuated pMTJs for high-speed, tunable TRNG applications, showing the importance of the stability of pMTJ device characteristics in achieving reliable, long-term performance.

Magnetic tunnel junctions↗
DOE OSTI2024

Machine learning without a processor: Emergent learning in a nonlinear analog network

Standard deep learning algorithms require differentiating large nonlinear networks, a process that is slow and power-hungry. Electronic contrastive local learning networks (CLLNs) offer potentially fast, efficient, and fault-tolerant hardware for analog machine learning, but existing implementations are linear, severely limiting their capabilities. These systems differ significantly from artificial neural networks as well as the brain, so the feasibility and utility of incorporating nonlinear elements have not been explored. Here, we introduce a nonlinear CLLN—an analog electronic network made of self-adjusting nonlinear resistive elements based on transistors. We demonstrate that the system learns tasks unachievable in linear systems, including XOR (exclusive or) and nonlinear regression, without a computer. We find our decentralized system reduces modes of training error in order (mean, slope, curvature), similar to spectral bias in artificial neural networks. The circuitry is robust to damage, retrainable in seconds, and performs learned tasks in microseconds while dissipating only picojoules of energy across each transistor. This suggests enormous potential for fast, low-power computing in edge systems like sensors, robotic controllers, and medical devices, as well as manufacturability at scale for performing and studying emergent learning.

Science & Technology - Other Topics↗
DOE OSTI2024

Neural units with time-dependent functionality

We show that the time-resolved dynamics of an underdamped harmonic oscillator can be used to do multifunctional computation, performing distinct computations at distinct times within a single dynamical trajectory. We consider the amplitude of an oscillator whose inputs influence its frequency. The activity of the oscillator at fixed times is a nonmonotonic function of its inputs, so it can solve problems such as XOR that are not linearly separable. The activity of the oscillator at fixed input is a nonmonotonic function of time, so it is multifunctional in a temporal sense, and able to carry out distinct nonlinear computations at distinct times within the same dynamical trajectory. We show that a single oscillator, observed at different times, can act as all of the elementary logic gates and perform binary addition, the latter usually implemented in hardware using five logic gates. We show that a set of n oscillators, observed at different times, can perform an arbitrary number of analog-to-n-bit digital conversions. We also show that oscillators can be trained by gradient descent to perform distinct classification tasks at distinct times. Computing with time-dependent functionality can be done in or out of equilibrium, and suggests a way of reducing the number of parameters or devices required to do nonlinear computations.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
NASA NTRS1979

Concurrent error detecting codes for arithmetic processors

A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes.

Lim, R. S.↗
NASA NTRS1989

Auto- and hetero-associative memory using a 2-D optical logic gate

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Chao, Tien-Hsin↗
NASA NTRS1992

RAID-2: Design and implementation of a large scale disk array controller

We describe the implementation of a large scale disk array controller and subsystem incorporating over 100 high performance 3.5 inch disk drives. It is designed to provide 40 MB/s sustained performance and 40 GB capacity in three 19 inch racks. The array controller forms an integral part of a file server that attaches to a Gb/s local area network. The controller implements a high bandwidth interconnect between an interleaved memory, an XOR calculation engine, the network interface (HIPPI), and the disk interfaces (SCSI). The system is now functionally operational, and we are tuning its performance. We review the design decisions, history, and lessons learned from this three year university implementation effort to construct a truly large scale system assembly.

Katz, R. H.↗
NASA NTRS2011

Range 7 Scanner Integration with PaR Robot Scanning System

An interface bracket and coordinate transformation matrices were designed to allow the Range 7 scanner to be mounted on the PaR Robot detector arm for scanning the heat shield or other object placed in the test cell. A process was designed for using Rapid Form XOR to stitch data from multiple scans together to provide an accurate 3D model of the object scanned. An accurate model was required for the design and verification of an existing heat shield. The large physical size and complex shape of the heat shield does not allow for direct measurement of certain features in relation to other features. Any imaging devices capable of imaging the entire heat shield in its entirety suffers a reduced resolution and cannot image sections that are blocked from view. Prior methods involved tools such as commercial measurement arms, taking images with cameras, then performing manual measurements. These prior methods were tedious and could not provide a 3D model of the object being scanned, and were typically limited to a few tens of measurement points at prominent locations. Integration of the scanner with the robot allows for large complex objects to be scanned at high resolution, and for 3D Computer Aided Design (CAD) models to be generated for verification of items to the original design, and to generate models of previously undocumented items. The main components are the mounting bracket for the scanner to the robot and the coordinate transformation matrices used for stitching the scanner data into a 3D model. The steps involve mounting the interface bracket to the robot's detector arm, mounting the scanner to the bracket, and then scanning sections of the object and recording the location of the tool tip (in this case the center of the scanner's focal point). A novel feature is the ability to stitch images together by coordinates instead of requiring each scan data set to have overlapping identifiable features. This setup allows models of complex objects to be developed even if the object is large and featureless, or has sections that don't have visibility to other parts of the object for use as a reference. In addition, millions of points can be used for creation of an accurate model [i.e. within 0.03 in. (=0.8 mm) over a span of 250 in. (=635 mm)].

Schuler, Jason↗
NASA NTRS2017

Using Dispersed Modes During Model Correlation

Using model dispersions as a starting point allows us to quickly adjust a model to reflect new test data: a) The analyst does a lot of work before the test to save time post-test. b) Creating 1000s of model dispersions to provide "coarse tuning," then use Attune to provide the "fine tuning." Successful model tuning on three structures: a) TAURUS. b) Ares I-X C) Cart (in backup charts). Mode weighting factors, matrix norm method, and XOR vs. MAC all play key roles in determining the BME. The BME process will be used on future tests: a) ISPE modal test (ongoing work). b) SLS modal test (mid 2018).

Stewart, Eric↗