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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science

This Perspective builds upon insights from the National Institute of Standards and Technology (NIST)-organized workshop, “Materials and Metrology Needs for Advanced Semiconductor Packaging Strategies,” held at the 35th annual Electronics Packaging Symposium in Binghamton, NY, on September 5, 2024. It outlines critical challenges and opportunities related to polymer-based “soft” materials in advanced semiconductor packaging, with emphasis on polymer science, measurement science (metrology), and the strategic development of Research-Grade Test Materials (RGTMs). These efforts, led by the NIST CHIPS team, aim to advance the fundamental understanding of structure-property-processing relationships, promote standardized guidelines and innovative methods for material characterization, and accelerate the development, qualification, and adoption of next-generation packaging materials. The Perspective also distills key insights from the panel discussion with industry experts, emphasizing the need for close collaboration among materials scientists, process engineers, and metrology experts to enable a holistic strategy, further highlighting the importance of cross-sector partnerships among industry, academia, and government to address pressing challenges in packaging materials and processes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

PV Inverter Systems Enabled by Monolithically Integrated SiC based Four Quadrant Power Switch (4-QPS) [BiDFET]

The purpose of this project was to develop a new breed of Power Conversion Systems (PCS) for PV integration that is enabled by the newly developed 4-Quadrant Single Die SiC Power Semiconductor Switches (4-QPS) or also referred to as “Bidirectional FET (BIDFET)”. This work includes semiconductor die development, advanced packaging, converter design, development, and testing of 4-QPS enabled hardware prototypes at 1 kW (for single phase residential application) and 10 kW (for three phase commercial application). The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS2014

Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.

Ghaffarian, Reza↗
DOE OSTI2022

Achieving American Leadership in the Semiconductors Supply Chain Factsheet

Semiconductors are a keystone technology that are essential for the operation of every electronic device, including those that are critical to a clean energy economy. The semiconductor industry has a complex, competitive, and highly integrated international supply chain in which the United States has historically enjoyed a dominant position, but where this position has been eroding over time. In 1995, 26% of global semiconductor manufacturing capacity was located in the United States; this had decreased to 10% by 2020. Investments in key semiconductor manufacturing technologies such as high-voltage power electronics, energy-efficient conventional devices, and advanced packaging point the way to secure a strong domestic semiconductor industrial base.

Source record↗
DOE OSTI2026

The Heterogeneous Integration of Electronic Components

Heterogeneous integration (HI) of electronics components is broadly recognized as a powerful and crucial enabler for the continued growth of computing and communication. From 2010 onwards, the value of HI is increasingly visible in the advanced packaging used in artificial intelligence, high-performance computing, smartphones and communications product implementations. In this Perspective, we argue that HI is crucial to semiconductors and more broadly to the continued evolution of computing and communications. We use leading-edge advanced packaging examples to represent the value, advancements and opportunities for HI. To succeed, it is critical to develop comprehensive HI roadmaps that inform collaborations across the design, manufacturing and reliability spectrum between systems architects, packaging and semiconductor technologists to common goals. Although this article does not provide a full roadmap, we instead detail additional parameters for artificial intelligence, smartphone and other cellular communication devices, and their constituent building blocks including interconnects, power electronics, photonics, thermal management, reliability, modelling and co-design, to foster greater collaboration opportunities among academia, research laboratories and industry.

42 ENGINEERING↗
NASA NTRS2011

Integrated Arrays on Silicon at Terahertz Frequencies

In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

silicon micromaching↗
DOE OSTI2020

Electronic Structure Theories of Singlet Fission and Multiple Exciton Generation (Final Report)

This DOE grant supported the development of electronic structure theory, algorithms, and computer programs for simulating singlet fission and multiple excision generation processes from Sept. 2013 to Aug. 2018 (which was terminated due to the PI’s departure from Northwestern University to industry). One of the main achievements is the development of the so-called active space decomposition (ASD) method hat describes exciton dynamics in organic semiconductors and spin dynamics in strongly correlated materials. The resulting software was interfaced with the Brilliantly Advanced General Electronic-structure Library (BAGEL) package and widely disseminated to the research community.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2024

AI-Enhanced Co-Design for Next-Generation Microelectronics: Innovating Innovation (Workshop Report)

The Artificial Intelligence Enhanced Co-Design for Next Generation Microelectronics virtual workshop was held April 4-5, 2023, and attended by subject matter experts from universities, industry, and national laboratories. This was the third in a series of workshops to motivate the research community to identify and address major challenges facing microelectronics research and production. The 2023 workshop focused on a set of topics from materials to computing algorithms, and included discussions on relevant federal legislation and such as the Creating Helpful Incentives to Produce Semiconductors and Science Act (CHIPS Act) which was signed into law in the summer of 2022. Talks at the workshop included edge computing in radiation environments, new materials for neuromorphic computing, advanced packaging for microelectronics, and new AI techniques. We also received project updates from several of the Department of Energy (DOE) microelectronics co-design projects funded in the fall of 2021, and from three of the Energy Frontier Research Centers (EFRCs) that had been funded in the fall of 2022. The workshop also conducted a set of breakout discussions around the five principal research directions (PRDs) from the 2018 Department of Energy workshop report: 1) define innovative material, device, and architecture requirements driven by applications, algorithms, and software; 2) revolutionize memory and data storage; 3) re-imagine information flow unconstrained by interconnects; 4) redefine computing by leveraging unexploited physical phenomena; 5) reinvent the electricity grid through new materials, devices, and architectures. We tasked each breakout group to consider one primary PRD (and other PRDs as relevant topics arose during discussions) and to address questions such as whether the research community has embraced co-design as a methodology and whether new developments at any level of innovation from materials to programming models requires the research community to reevaluate the PRDs developed back in 2018.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2001

Electronics for Low-Temperature Space Operation Being Evaluated

Electronic components and systems capable of low-temperature operation are needed for many future NASA missions where it is desirable to have smaller, lighter, and cheaper (unheated) spacecraft. These missions include Mars (-20 to -120 C) orbiters, landers, and rovers; Europa (-150 C) oceanic exploratory probes and instrumentation; Saturn (-183 C) and Pluto (-229 C) interplanetary probes. At the present, most electronic equipment can operate down to only -55 C. It would be very desirable to have electronic components that expand the operating temperature range down to -233 C. The successful development of these low-temperature components will eventually allow space probes and onboard electronics to operate in very cold environments (out as far as the planet Pluto). As a result, radioisotope heating units, which are used presently to keep space electronics near room temperature, will be reduced in number or eliminated. The new cold electronics will make spacecraft design and operation simpler, more flexible, more reliable, lighter, and cheaper. Researchers at the NASA Glenn Research Center are evaluating potential commercial off-the- shelf devices and are developing new electronic components that will tolerate operation at low temperatures down to -233 C. This work is being carried out mainly inhouse and also through university grants and commercial contracts. The components include analog-to-digital converters, semiconductor switches, capacitors, dielectric and packaging material, and batteries. For example, the effect of low temperature on the capacitance of three different types of capacitors is shown in the graph. Using these advanced components, system products will be developed, including dc/dc converters, battery charge/discharge management systems, digital control electronics, transducers, and sensor instrumentation.

Patterson, Richard L.↗
NASA NTRS2011

Terahertz Array Receivers with Integrated Antennas

Highly sensitive terahertz heterodyne receivers have been mostly single-pixel. However, now there is a real need of multi-pixel array receivers at these frequencies driven by the science and instrument requirements. In this paper we explore various receiver font-end and antenna architectures for use in multi-pixel integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies has progressed very well over the past few years. Novel stacking of micro-machined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages has made it possible to design multi-pixel heterodyne arrays. One of the critical technologies to achieve fully integrated system is the antenna arrays compatible with the receiver array architecture. In this paper we explore different receiver and antenna architectures for multi-pixel heterodyne and direct detector arrays for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

direct detector arrays↗
NASA NTRS2003

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

Beheim, Glenn M.↗
NASA NTRS1988

Power components for the space station 20-kHz power distribution system

Since 1984, NASA Lewis Research Center was developing high power, high frequency space power components as part of The Space Station Advanced Development program. The purpose of The Advanced Development program was to accelerate existing component programs to ensure their availability for use on the Space Station. These components include a rotary power transfer device, remote power controllers, remote bus isolators, high power semiconductor, a high power semiconductor package, high frequency-high power cable, high frequency-high power connectors, and high frequency-high power transformers. All the components were developed to the prototype level and will be installed in the Lewis Research Center Space Station power system test bed.

Renz, David D.↗
NASA NTRS1988

Power components for the Space Station 20-kHz power distribution system

Since 1984, NASA Lewis Research Center was developing high power, high frequency space power components as part of The Space Station Advanced Development program. The purpose of the Advanced Development program was to accelerate existing component programs to ensure their availability for use on the Space Station. These components include a rotary power transfer device, remote power controllers, remote bus isolators, high power semiconductor, a high power semiconductor package, high frequency-high power cable, high frequency-high power connectors, and high frequency-high power transformers. All the components were developed to the prototype level and will be installed in the Lewis Research Center Space Station power system test bed.

Renz, David D.↗
DOE OSTI2026

Advanced Power Electronics and Electric Machines

NLR's advanced power electronics and electric machines (APEEM) research group develops world-class experimental and modeling capabilities to design and evaluate efficient and reliable power electronics and electric machines, as well as innovative thermal management systems to maximize their performance. They also design, fabricate, and characterize advanced power electronics packaging and are developing state-of-health monitoring techniques.

25 ENERGY STORAGE↗
NASA NTRS1999

Nano-Satellite Avionics

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

Culver, Harry↗
DOE OSTI2024

New Roadmap for Microelectronics: Charting the Semiconductor Industry's Path Over the Next 5, 10, and 20 Years

In the past, the role of strategic planning for semiconductor industry was met by the International Technology Roadmap for Semiconductors (ITRS), serving as a guiding light that provided manufacturers, designers, equipment suppliers, and researchers with direction years in advance. By providing a common framework for coordination across semiconductor industry stakeholders, technology development efforts were efficient and aligned. However, the dissolution of the ITRS in 2015 left a void, leading to years of disjointed efforts. Recognizing the need for unified guidance, the industry rallied for the creation of a new strategic plan, the Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap (2023) was developed, through the efforts of hundreds of industry, academic and government experts, to provide detailed strategies for achieving these goals. This comprehensive plan outlines ambitious goals for the industry's future.

HPC, Roadmap, AI, Liquid Cooling, Power, Silicon, ↗
NASA NTRS2014

Advanced CMOS Radiation Effects Testing and Analysis

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

cmos↗
DOE OSTI2026

Review of Ultrafast Switching Power Modules: Trends, Challenges, and Technical Solutions

Benefiting from the superior properties of wide-bandgap semiconductor materials, wide-bandgap power devices demonstrate exceptional switching performance, enabling more efficient and compact power electronics systems. However, ultrafast switching poses challenges to the reliability of the system in terms of severe oscillations and voltage overshoot, electromagnetic interference, and increased risk of partial discharge. By developing advanced power module packaging for fast-switching power devices, the above-mentioned challenges can be mitigated at the packaging level, enabling the full utilization of the fast-switching capability of wide-bandgap devices. Meanwhile, such technology also lays the groundwork for packaging next-generation power devices with even higher blocking voltage and faster switching speed. In this paper, a comprehensive review of ultrafast switching power modules has been made, including the benefits and status of ultrafast switching power modules, challenges brought by ultrafast switching, and promising technologies to address these challenges. In addition, future development trends and research gaps are also discussed in this paper. Furthermore, this review can serve as a reference for future wide-bandgap power module packaging design.

24 POWER TRANSMISSION AND DISTRIBUTION↗