Advanced analog signal processing for fuzing Final Report CRADA No. TC-1306-96
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99 GENERAL AND MISCELLANEOUS↗
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A front-end readout Detector Board for the OpenPET electronics system
Here, we present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is "time stamped" by a time-to-digital converter (TDC) implemented inside the FPGA. In conclusion, this digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.
47 OTHER INSTRUMENTATION↗
Coherent radar receiver that comprises a sigma delta modulator
Described herein are various technologies relating to processing a coherent signal. A receiver is configured to receive an analog signal, and process the analog signal to generate an input analog signal. The input analog signal has been modulated according to a suitable modulation sequence. A coherent signal sampler coherently samples the modulation sequence, and the result of such sampling is in turn used to demodulate the input analog signal. The resultant signal is then passed to a sigma delta modulator, where it is converted to digital form.
47 OTHER INSTRUMENTATION↗
Toward Mixed Analog-Digital Quantum Signal Processing: Quantum AD/DA Conversion and the Fourier Transform
Signal processing stands as a pillar of classical computation and modern information technology, applicable to both analog and digital signals. Recently, advancements in quantum information science have suggested that quantum signal processing (QSP) can enable more powerful signal processing capabilities. However, the developments in QSP have primarily leveraged digital quantum resources, such as discrete-variable (DV) systems like qubits, rather than analog quantum resources, such as continuous-variable (CV) systems like quantum oscillators. Consequently, there remains a gap in understanding how signal processing can be performed on hybrid CV-DV quantum computers. Here we address this gap by developing a new paradigm of mixed analog-digital QSP. We demonstrate the utility of this paradigm by showcasing how it naturally enables analog-digital conversion of quantum signals—specifically, the transfer of states between DV and CV quantum systems. We then show that such quantum analog-digital conversion enables new implementations of quantum algorithms on CV-DV hardware. This is exemplified by realizing the quantum Fourier transform of a state encoded on qubits via the free-evolution of a quantum oscillator, albeit with a runtime exponential in the number of qubits due to information theoretic arguments. Collectively, this work marks a significant step forward in hybrid CV-DV quantum computation, providing a foundation for scalable analog-digital signal processing on quantum processors.
42 ENGINEERING↗
Smart Pixels: In-pixel AI for on-sensor data filtering
We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.
Parpillon, Benjamin↗
Smart Pixels: In-pixel AI for on-sensor data filtering
We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Using pulse shape analysis to improve the position resolution of a resistive anode microchannel plate detector
Digital signal processing techniques were employed to investigate the joint use of charge division and risetime analyses for the resistive anode (RA) coupled to a microchannel plate detector (MCP). In contrast to the typical approach of using the relative charge at each corner of the RA, this joint approach results in a significantly improved position resolution. A conventional charge division analysis utilizing analog signal processing provides a measured position resolution of 170 μm (FWHM). By using the correlation between risetime and position we were able to obtain a measured resolution of 92μm (FWHM), corresponding to an intrinsic resolution of 64μm (FWHM) for a single Z-stack MCP detector.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
A Half-Bridge On-State Voltage Sensor for In-Situ Measurements
Current prognostics for life expectancy of power semiconductors utilize off-line measurements of the on-state resistance. Presented is a half-bridge (HB) on-state voltage (VON) sensor capable of being utilized for in-situ measurements enabling continuous and real-time monitoring of the on-state resistance. The design provides a single VON measurement output that contains independent VON information of both high and low side devices in a HB leg. The measurement output is referenced from the middle point of the HB and combines the two complementary VON sensing outputs. This system reduces the number of components, required number of analog signal processing circuits, and ADC channels for in-situ health monitoring of a power electronics system. These reductions will facilitate integration of the VON sensor with the gate driver board and achieve low system profile. The experimental results demonstrate the proposed VON measurements while switching with inductive and resistive loads.
Roy, Chondon↗
Upgrade to Fixed and Translating Scintillation-based Loss Detector System in the Fermilab Drift Tube Linac
The closed-off structure of the Fermilab Drift Tube Linac precludes a robust array of instrumentation from directly monitoring the H- beam that is accelerated from 750 keV to 116 MeV. To improve beam tuning and operational assessment of Drift Tube Linac performance, scintillator-based loss monitors were previously installed along the exterior of the first two accelerating cavities to assess low energy beam losses. Here we present a recent upgrade to the loss monitor system, including significant improvements in analog signal processing to address baseline-interfering noise; digitization of the signals to enable regular operational use and tuning; and a new remote operation upgrade of the translating loss monitor with precise positioning of the loss monitor along its nine-foot track. Data from the fixed and translating detectors collected under varying beam conditions validate the utility of the upgrade.
Chen, E. V. [Fermilab]↗
Upgrade to Fixed and Translating Scintillation-Based Loss Detector System in the Fermilab Drift Tube Linac
The closed-off structure of the Fermilab Drift Tube Linac precludes a robust array of instrumentation from directly monitoring the H- beam that is accelerated from 750 keV to 116 MeV. To improve beam tuning and op-erational assessment of Drift Tube Linac performance, scintillator-based loss monitors were previously installed along the exterior of the first two accelerating cavities to assess low energy beam losses. Here we present a recent upgrade to the loss monitor system, including significant improvements in analog signal processing to address baseline-interfering noise; digitization of the signals to enable regular operational use and tuning; and a new remote operation upgrade of the translating loss monitor with precise positioning of the loss monitor along its nine-foot track. Data from the fixed and translating de-tectors collected under varying beam conditions validate the utility of the upgrade.
Chen, Erin V. [Fermilab] (ORCID:0000000215467899)↗
THE FRONTEND ANALOG AND DIGITAL SIGNAL PROCESSING ELECTRONICS FOR THE DRIFT CHAMBERS OF THE STANFORD LARGE DETECTOR
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Haller, G.↗
Fractional delay filter for a digital signal processing system
A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.
Stanley, Dennis L.↗
Multi-channel front-end ASIC for a 3D position-sensitive detector
Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.
47 OTHER INSTRUMENTATION↗
A Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications
This study reports a 24×57 correlation filter system for object tracking applications. While digital interfacing of the input and output data enabled a standard and flexible way of communication with pre- and post-processing digital blocks, the multiply-accumulate (MAC) operations were performed in the analog domain to save power and area. The proposed system utilizes non-volatile floating-gate memories to store filter coefficients. The chip was fabricated in a 0.13- μm CMOS process and occupies 3.23 mm 2 of silicon area. The system dissipates 388.4 μW of power at a throughput of 11.3 kVec/s, achieving an energy efficiency of 25.2 pJ/MAC. Finally, experimental results for a custom filter designed to detect vehicles are presented.
97 MATHEMATICS AND COMPUTING↗
In-pixel AI for lossy data compression at source for X-ray detectors
Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. Here, we compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50$×$ compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70$×$ compression, adds 30 clock cycle latency, and results in a similar area increase.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Signal Processing for a Multi-channel Analog Data Acquisition Instrumentation System for an MEG Atomic Magnetometer.
Abstract not provided.
Goldberg, Joshua David↗
Signal digitizing system and method based on amplitude-to-time optical mapping
A signal digitizing system and method based on analog-to-time optical mapping, optically maps amplitude information of an analog signal of interest first into wavelength information using an amplitude tunable filter (ATF) to impress spectral changes induced by the amplitude of the analog signal onto a carrier signal, i.e. a train of optical pulses, and next from wavelength information to temporal information using a dispersive element so that temporal information representing the amplitude information is encoded in the time domain in the carrier signal. Optical-to-electrical conversion of the optical pulses into voltage waveforms and subsequently digitizing the voltage waveforms into a digital image enables the temporal information to be resolved and quantized in the time domain. The digital image may them be digital signal processed to digitally reconstruct the analog signal based on the temporal information with high fidelity.
47 OTHER INSTRUMENTATION↗
Design of a readout circuit incorporating a 12-bit analog-to-digital converter for cooled infrared focal plane array
The infrared focal plane array (IRFPA) is gradually becoming more systematic. In order to enhance the signal processing capabilities, analog-to-digital converters (ADC) integrated into the readout integrated circuit (ROIC) is an important development trend. However, the cryogenic effects of MOSFET devices will affect the conversion accuracy of the ADC at 77 K. In this paper, the main parameters of MOSFET are extracted at 77 K in 0.18 μm CMOS process, and a cryogenic model is established. Based on this, a digital ROIC is designed, which integrates a 12-bit single-slope integral ADC in pixel unit. By applying continuous integral ramp generator and mixed-voltage comparator, a high-linearity and low-power consumption single-slope ADC is realized for the cooled readout circuit. The measured dynamic effective number of bits of the ADC at 77 K is 10.92 bits, the static no-missing code resolution reaches 11.99 bits, the maximum differential nonlinear |DNL| < 1LSB and maximum integral nonlinear |INL| < 1LSB. This paper realizes the design of a digital ROIC for IRFPA and improves the simulation accuracy at 77 K.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗