Lessons Learned in Outsourcing Board Assemblies
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lessons outsourcing board assemblies↗
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Workshop H: Building Reliable Circuit Board Assemblies - The Lessons Learned
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Printed Circuit Boards↗
Printed Circuit Board Assembly for Use in Space Missions
An electronic assembly for use in space missions that includes a PCB and one or more multi-pin CGA devices coupled to the PCB. The PCB has one or more via-in-pad features and each via-in-pad feature comprises a land pad configured to couple a pin of the one or more multi-pin CGA devices to the via. The PCB also includes a plurality of layers arranged symmetrically in a two-halves configuration above and below a central plane of the PCB.
Petrick, David J.↗
Life Cycle Analysis of a SpaceCube Printed Circuit Board Assembly Using Physics of Failure Methodologies
In this reliability life cycle evaluation of the SpaceCube 2.0 processor card, a partially populated version of the card is being evaluated to determine its durability with respect to typical GSFC mission loads.
Virtual Qualification↗
Design requirements for rigid printed wiring boards and assemblies. NASA Handbook
The NASA requirements for assuring reliable rigid printed wiring board design are prescribed. Basic considerations necessary to assure reliable rigid printed wiring board design are described and incorporated.
Source record↗
Revised Point-spread Functions for the Atmospheric Imaging Assembly on board the Solar Dynamics Observatory
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Stefan J. Hofmeister↗
Column Grid Array Rework for High Reliability
Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.
high reliability↗
High-Rate Ka-Band Modulator for the NISAR Mission
In order to meet ever-increasing data return requirements, more satellites are using the near-Earth Ka-band (25.5 – 27.0 GHz) to achieve higher downlink rates. The paper discusses the Universal Space Transponder - Ka-band Modulator (UST-KaM) developed at the NASA Jet Propulsion Laboratory for the NASA-ISRO SAR (NISAR) mission, which is capable of transmitting up to 1.74 Gbps with 7/8 LDPC encoding. The UST-KaM utilizes OQPSK with both baseband and RF filtering to contain the 1 Gsps transmission spectrum within the 1.5 GHz Ka-band, even with the use of an external, saturated amplifier. Due to the high data rates involved, several technical hurdles were overcome in both the digital and RF designs. The UST-KaM is a software defined radio with two digital circuit board assemblies: a low speed housekeeper board for commanding and telemetry, and a high-rate signal processing board known as the Signal Processing Module (SPM). The SPM receives data from the spacecraft via a SERDES interface at up to 2 Gbps, processes and encodes the data using a Xilinx Virtex-5 FPGA, and produces 1 Gsps OQPSK I and Q waveforms via synchronized, multiplexed DACs. The RF Electronics in the UST-KaM employ a heterodyne architecture in which the I/Q digital waveforms are filtered and then up-converted using a sub-harmonic IQ mixer. The LO of the converter, which is included in the exciter assembly, is at 13.125GHz, and the RF output is a 26.25GHz carrier which is modulated with the OQPSK waveforms. The output of the mixer is then filtered using low loss quartz thinfilm edge coupled Chebyshev filters and amplified through a series of low gain Ka-Band amplifiers. The exciter assembly also has a 2GHz, low-phase-noise, PLL synthesizer to supply the clock to the DACs for the high rate digital waveforms.
Spurgers, Carl↗
Modified eddy current probe having a faraday shield
A modified eddy current (MEC) probe includes a probe body having a bore formed therein. A printed circuit board (PCB) assembly includes a circuit board defining a plane, has a plurality of electronic components mounted thereon, and is configured for mounting within the bore of the probe body. A coil board assembly is electrically connected to the PCB assembly, defines a plane, and includes a first coil board layer, a second coil board layer bonded to the first coil board layer, a transmitter coil formed on an outside surface of the first coil board layer, a Faraday shield formed on an outside surface of the second coil board layer, and a sensor coil formed on one of an inside surface of the first coil board layer and the second coil board layer, such that the sensor coil is positioned between the first coil board layer and the second coil board layer. The plane of the coil board assembly is arranged orthogonally to the plane of the circuit board.
47 OTHER INSTRUMENTATION↗
Investigation of Solder Cracking Problems on Printed Circuit Boards
A Solder Committee designated to investigate a solder cracking phenomena occurring on the SATURN electrical/electronic hardware found the cause to be induced stress in the soldered connections rather than faulty soldering techniques. The design of the printed circuit (PC) board assemblies did not allow for thermal expansion of the boards that occurred during normal operation. The difference between the thermal expansion properties of the boards and component lead materials caused stress and cracking in the soldered connections. The failure mechanism and various PC boards component mounting configurations are examined in this report. Effective rework techniques using flanged tubelets, copper tubelets, and soft copper wiring are detailed. Future design considerations to provide adequate strain relief in mounting configurations are included to ensure successful solder terminations.
CIRCUIT BOARD↗
Training Circuit Boards
Young Electronics Company's new product is a testboard developed by the Jet Propulsion Laboratory as a tool for training and qualifying personnel in board assembly and in the art of soldering components without damaging boards or components. The boards are used for pre- employment testing and employee requalification.
Source record↗
Assembling Multicolor Printing Plates
Improved joining method uses wave-soldering techniques developed for integrated-circuit-board assemblies. Thermosetting plastic is replaced by wave soldering, which applies a thin even coat of solder to mating copper surfaces. This is done after ink holes and channels have been protected by water-soluble, high-temperature solder mask which prevents wetting and clogging.
Waters, W. J.↗
Achieving Improved Reliability with Failure Analysis
Reliability is the ability of a product to properly function, within specified performance limits, for a specified period of time, under the life cycle application conditions. Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and sophisticated supply chains, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes and, customer dissatisfaction due to recurring failures. The PDC (Professional Development Course) starts with an introduction to reliability concepts, physics of failure and an overview of failure mechanisms that affect PCBs (Printed Circuit Boards), PCBAs (Printed Circuit Board Assembly) and components. The PDC then dives into root cause hypothesizing techniques (Pareto, FMEA (Failure Modes and Effects Analysis), fishbone (Cause-And-Effect Diagram), FTA (Fault Tree Analysis)), non-destructive and destructive analysis and, materials characterization will be discussed. Numerous failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies. What Attendees will Learn: Topics include: Overview of Reliability Concepts Failure mechanisms of electronic products Root cause analysis Failure analysis techniques -Non-destructive techniques (optical, CSAM (Confocal Scanning Electron Microscopy) etc.) -Destructive analysis (DPA (Destructive Physical Analysis), Decap (Decapsulation), FIB (Focused Ion Beam) etc.) -Materials characterization (XRF (X-Ray Fluorescence) , EDS (Error Detection Sequential), TMA/DSC (Thermal Mechanical Analysis/Differential Scanning Calorimetry) etc.)
PCB quality↗
Experimental Assembly and Sterilization Laboratory - Clothing study
Effect of clothing on control of microorganism shedding from worker constructing printed circuit board assembly
Botan, E. A.↗
Reliability of CGA/LGA/HDI Package Board/Assembly (Revision A)
This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of 55 C to maximum temperatures of either 100 C or 125 C with slow ramp-up rate (3 C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects' use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight.
Ghaffarian, Reza↗
Reliability of CGA/LGA/HDI Package Board/Assembly
This follow-up report presents reliability test results conducted by thermal cycling of five CGA assemblies evaluated under two extreme cycle profiles, representative of use for high-reliability applications. The thermal cycles ranged from a low temperature of −55°C to maximum temperatures of either 100°C or 125°C with slow ramp-up rate (3°C/min) and dwell times of about 15 minutes at the two extremes. Optical photomicrographs that illustrate key inspection findings of up to 200 thermal cycles are presented. Other information presented include an evaluation of the integrity of capacitors on CGA substrate after thermal cycling as well as process evaluation for direct assembly of an LGA onto PCB. The qualification guidelines, which are based on the test results for CGA/LGA/HDI packages and board assemblies, will facilitate NASA projects’ use of very dense and newly available FPGA area array packages with known reliably and mitigation risks, allowing greater processing power in a smaller board footprint and lower system weight.
Ghaffarian, Reza↗
Application of PoF Based Virtual Qualification Methods for Reliability Assessment of Mission Critical PCBs
Reliability is the ability of a product to perform the function for which it was intended for a specified period of time (or cycles) for a given set of life cycle conditions. In today's compressed mission development cycles where designing, building and testing the physical models has to occur in a matter of months not years, Projects don't have the luxury of iteratively building and testing those models. Physics of failure (PoF) is an engineering-based approach to reliability that begins with an understanding of materials, processes, physical interactions, degradation and failure mechanisms, as well as identifying failure models. The PoF approach uses modeling and simulation to qualify a design and manufacturing process, with the ultimate intent of eliminating failures early in the design process by addressing the root cause. The physics-of-failure analysis proactively incorporates reliability into the design process by establishing a scientific basis for evaluating new materials, structures and technologies. Virtual physics-of-failure modeling allows engineers to determine if new technological node can be added to an existing system. This presentation will illustrate an application of a PoF based tool during the initial phases of a printed circuit board assembly development and how the NASA GSFC team was able to dynamically study the effects of electronics parts and printed circuit board material configuration changes under simulated thermal and vibrational stresses
Electronics packaging↗
Application of PoF Based Virtual Qualification Methods for Reliability Assessment of Mission Critical PCBs
Reliability is the ability of a product to perform the function for which it was intended for a specified period of time (or cycles) for a given set of life cycle conditions. In today's compressed mission development cycles where designing, building and testing the physical models has to occur in a matter of months not years, Projects don't have the luxury of iteratively building and testing those models. Physics of failure (PoF) is an engineering-based approach to reliability that begins with an understanding of materials, processes, physical interactions, degradation and failure mechanisms, as well as identifying failure models. The PoF approach uses modeling and simulation to qualify a design and manufacturing process, with the ultimate intent of eliminating failures early in the design process by addressing the root cause. The physics-of-failure analysis proactively incorporates reliability into the design process by establishing a scientific basis for evaluating new materials, structures and technologies. Virtual physics-of-failure modeling allows engineers to determine if new technological node can be added to an existing system. This presentation will illustrate an application of a PoF based tool during the initial phases of a printed circuit board assembly development and how the NASA GSFC team was able to dynamically study the effects of electronics parts and printed circuit board material configuration changes under simulated thermal and vibrational stresses.
Physics of Failure↗