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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Bypass diode integration

Protective bypass diodes and mounting configurations which are applicable for use with photovoltaic modules having power dissipation requirements in the 5 to 50 watt range were investigated. Using PN silicon and Schottky diode characterization data on packaged diodes and diode chips, typical diodes were selected as representative for each range of current carrying capacity, an appropriate heat dissipating mounting concept along with its environmental enclosure was defined, and a thermal analysis relating junction temperature as a function of power dissipation was performed. In addition, the heat dissipating mounting device dimensions were varied to determine the effect on junction temperature. The results of the analysis are presented as a set of curves indicating junction temperature as a function of power dissipation for each diode package.

Shepard, N. F., Jr.↗
NASA NTRS1984

The integration of bypass diodes with terrestrial photovoltaic modules and arrays

Bypass diodes are often required to limit the potential for reverse voltage 'hot-spot' heating in high voltage arrays or in arrays that undergo periodic operation near the short-circuit point. In addition, when properly applied, bypass diodes can minimize the effect of shadowing and various internal module failures on the array energy output. This paper discusses the mechanical and electrical integration of bypass diodes beginning with the array-level considerations which influence the selection of an implementation approach. Concepts for the mounting of these diodes, both internally within the module encapsulant and externally to the exposed rear surface of the module, are described. Factors affecting the reliability of bypass diodes, including the control of junction temperature through adequate heat sinking and the derating of reverse voltage, are discussed.

Shepard, N. F., Jr.↗
NASA NTRS1983

Photovoltaic module bypass diode encapsulation

The design and processing techniques necessary to incorporate bypass diodes within the module encapsulant are presented. The Semicon PN junction diode cells were selected. Diode junction to heat spreader thermal resistance measurements, performed on a variety of mounted diode chip types and sizes, have yielded values which are consistently below 1 deg C per watt, but show some instability when thermally cycled over the temperature range from -40 to 150 deg C. Three representative experimental modules, each incorporating integral bypass diode/heat spreader assemblies of various sizes, were designed. Thermal testing of these modules enabled the formulation of a recommended heat spreader plate sizing relationship. The production cost of three encapsulated bypass diode/heat spreader assemblies were compared with similarly rated externally mounted packaged diodes. It is concluded that, when proper designed and installed, these bypass diode devices will improve the overall reliability of a terrestrial array over a 20 year design lifetime.

Shepard, N. J., Jr.↗
NASA NTRS1983

Design and selection of bypass diodes

Topics concerning the design and use of bypass diodes are investigated. Energy output, service life, safety, cell mounting approach, thermal capability, and cost analysis are also considered.

Shepard, N. F., Jr.↗
NASA NTRS2016

Bypass Diode Temperature Tests of a Solar Array Coupon Under Space Thermal Environment Conditions

Tests were performed on a 56-cell Advanced Triple Junction solar array coupon whose purpose was to determine margin available for bypass diodes integrated with new, large multi-junction solar cells that are manufactured from a 4-inch wafer. The tests were performed under high vacuum with coupon back side thermal conditions of both cold and ambient. The bypass diodes were subjected to a sequence of increasing discrete current steps from 0 Amp to 2.0 Amp in steps of 0.25 Amp. At each current step, a temperature measurement was obtained via remote viewing by an infrared camera. This paper discusses the experimental methodology, experiment results, and the thermal model.

Wright, Kenneth H., Jr.↗
NASA NTRS1985

Development of design criteria and qualification tests for bypass diodes in photovoltaic applications

Design criteria have been developed for bypass diodes in p-n and Schottky barrier in photovoltaic applications. A test method for assessing conformity to the design criteria is described. Junction temperatures are defined in terms of expected worst-case field conditions, including ambient temperature and solar irradiance on the photovoltaic module. The rating criteria address the maximum allowable current and heat-sink characteristics of diodes mounted inside or outside the photovoltaic module. The method establishes worst-case module-to-diode thermal interfaces and may be adapted for laboratory or field-site experiments. A list of the design criteria is given.

Otth, D. H.↗
NASA NTRS1991

Integral bypass diodes in an amorphous silicon alloy photovoltaic module

Thin-film, tandem-junction, amorphous silicon (a-Si) photovoltaic modules were constructed in which a part of the a-Si alloy cell material is used to form bypass protection diodes. This integral design circumvents the need for incorporating external, conventional diodes, thus simplifying the manufacturing process and reducing module weight.

Hanak, J. J.↗
NASA NTRS2016

By-Pass Diode Temperature Tests of a Solar Array Coupon Under Space Thermal Environment Conditions

Tests were performed on a 56-cell Advanced Triple Junction solar array coupon whose purpose was to determine margin available for bypass diodes integrated with new, large multi-junction solar cells that are manufactured from a 4-inch wafer. The tests were performed under high vacuum with cold and ambient coupon back-side. The bypass diodes were subjected to a sequence of increasing discrete current steps from 0 Amp to 2.0 Amp in steps of 0.25 Amp. At each current step, a temperature measurement was obtained via remote viewing by an infrared camera. This paper discusses the experimental methodology, including the calibration of the thermal imaging system, and the results.

Wright, Kenneth H., Jr.↗
NASA NTRS2018

Insights into Space Solar Cell Durability Using SPICE Simulation Seeded by Current-Voltage Characteristics Parametrized Using the Lambert W Special Function

We developed and validated an automated routine for the fitting of I-V curve data to the single diode model according to an exact analytical solution. Our fitting routine was validated to show good noise immunity and high accuracy usingsimulated values from LTSPICE. We are thus able to automate parameter extraction from a dataset or arbitrary size. This parameterization allows for better simulation of performance of real cells and arrays and provides utility for a host of applications relevant to space arrays. We will use this methodology to determine the array performance of radiated cells over time, and simulate the performance of the arrays with bypass diodes and power electronics.

Solar Cell↗
NASA NTRS1976

Gate assisted turn-off thyristor with cathode shunts and dynamic gate

A 1,000-V, 200-A gate-assisted turn-off thyristor (GATT) is described, whose design features include an interdigitated shunted cathode, a dynamic gate, a means for optimizing the carrier lifetime level, and a bypass diode. The device physics of gate-assisted turn-off are reviewed. Based on this, improvements in the design are described. It is shown that a prime failure mode can be eliminated and that the gate-assist signal voltage can be substantially decreased by employing a shunted cathode emitter. The test data show excellent turn-on characteristics due to the dynamic gate and the long perimeter of the edge of the main cathode. Turn-off times as short as 3 microsec are obtained. The combination of controlling the carrier lifetime with a precisely controlled and easily variable irradiation dose of high energy electrons with gate assist current provides for simple, precision tailoring of the device characteristics to the intended application.

Schlegel, E. S.↗
NASA NTRS1982

Reliability and performance experience with flat-plate photovoltaic modules

Statistical models developed to define the most likely sources of photovoltaic (PV) array failures and the optimum method of allowing for the defects in order to achieve a 20 yr lifetime with acceptable performance degradation are summarized. Significant parameters were the cost of energy, annual power output, initial cost, replacement cost, rate of module replacement, the discount rate, and the plant lifetime. Acceptable degradation allocations were calculated to be 0.0001 cell failures/yr, 0.005 module failures/yr, 0.05 power loss/yr, a 0.01 rate of power loss/yr, and a 25 yr module wear-out length. Circuit redundancy techniques were determined to offset cell failures using fault tolerant designs such as series/parallel and bypass diode arrangements. Screening processes have been devised to eliminate cells that will crack in operation, and multiple electrical contacts at each cell compensate for the cells which escape the screening test and then crack when installed. The 20 yr array lifetime is expected to be achieved in the near-term.

Ross, R. G., Jr.↗
NASA NTRS1983

Hot-spot heating in central-station arrays

Hot spot tests performed on the Sacramento Municipal Utility District (SMUD) verificaton array show that current imbalance occurs, resulting in significant hot spot heating. One cause of current imbalance is differences in the average shunt resistances of parallel cell strings due to cell shunt resistance variations. In depth hot spot tests are performed on the verification array with bypass diodes. The tests had several objectives: (1) a comparison of hot spot temperatures achieved under field conditions with those obtained with the present laboratory hot spot test using similar modules; (2) an assessment of current imbalance versus cross tie frequency; and (3) an assessment of different shadow patterns and shadow densities. Instrumented modules are used to vary the number of cross ties and to measure the test-cell current and back-bias voltage. The widths, lengths, and densities of the shadows are varied to maximize the back bias voltage at maximum power current. An infrared camera is used to indicate the existence of hot spots and estimate temperature increases in conjunction with thermocouples. The results of these hot spot tests indicate a sensitivity of back bias heating to the shadow size (amount of cell coverage) and density.

Gonzalez, C. C.↗
NASA NTRS1983

Source circuit design considerations

The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.

Noel, G. T.↗
NASA NTRS1985

Hot-spot heating susceptibility due to reverse bias operating conditions

Because of field experience (indicating that cell and module degradation could occur as a result of hot spot heating), a laboratory test was developed at JPL to determine hot spot susceptibility of modules. The initial hot spot testing work at JPL formed a foundation for the test development. Test parameters are selected as follows. For high shunt resistance cells, the applied back bias test current is set equal to the test cell current at maximum power. For low shunt resistance cells, the test current is set equal to the cell short circuit current. The shadow level is selected to conform to that which would lead to maximum back bias voltage under the appropriate test current level. The test voltage is determined by the bypass diode frequency. The test conditions are meant to simulate the thermal boundary conditions for 100 mW/sq cm, 40C ambient environment. The test lasts 100 hours. A key assumption made during the development of the test is that no current imbalance results from the connecting of multiparallel cell strings. Therefore, the test as originally developed was applicable for single string case only.

Gonzalez, C. C.↗
NASA NTRS1986

Crystalline-silicon photovoltaics summary module design and reliability

The evolution of the design and reliability of solar modules was described. Design requirements involved 14 different considerations, including residential building and material electrical codes, wind-loading, hail impact, operating temperature levels, module flammability, and interfaces for both the array structure and the operation of the system. Reliability research involved in diverse investigations including glass-fracture strength, soiling levels, electrochemical corrosion, and bypass-diode qualification tests. Based on these internationally recognized studies, performance assessments, and failure analyses, the Flat-plate Solar Array Project in its 11-year duration served to nuture the development of 45 different solar module designs from 15 PV manufacturers.

Ross, R. G., Jr.↗
NASA NTRS1987

Concentrator hot-spot testing, phase 1

Results of a study to determine the hot-spot susceptibility of concentrator cells, to provide a hot-spot qualification test for concentrator modules, and to provide guidelines for reducing hot-spot susceptibility are presented. Hot-spot heating occurs in a photovoltaic module when the short-circuit current of a cell is lower than the string operating current forcing the cell into reverse bias with a concurrent power dissipation. Although the basis for the concentrator module hot-spot qualification test is the test developed for flat-plate modules, issues, such as providing cell illumination, introduce additional complexities into the testing procedure. The same general guidelines apply for protecting concentrator modules from hot-spot stressing as apply to flat-plate modules. Therefore, recommendations are made on the number of bypass diodes required per given number of series cells per module or source circuit. In addition, a new method for determining the cell temperature in the laboratory or in the field is discussed.

Gonzalez, C. C.↗
NASA NTRS1985

Hot-spot durability testing of amorphous cells and modules

This paper discusses the results of a study to determine the hot-spot susceptibility of amorphous-silicon (a-Si) cells and modules, and to provide guidelines for reducing that susceptibility. Amorphous-Si cells are shown to have hot-spot susceptibility levels similar to crystalline-silicon (C-Si) cells. This premise leads to the fact that the same general guidelines must apply to protecting a-Si cells from hot-spot stressing that apply to C-Si cells. Recommendations are made on ways of reducing a-Si module hot-spot susceptibility including the traditional method of using bypass diodes and a new method unique to thin-film cells, limiting the string current by limiting cell area.

Gonzalez, Charles↗