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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

One Dimensional Capacitive Loading in a Frequency Selective Surface for Low Profile Antenna Applications

In this paper, the impact of adding discrete capacitive loading along one dimension of a frequency selective surface for low profile antenna applications is presented for the first time. The measured data demonstrates comparable performance between a non-loaded and a capacitively-loaded FSS with a significant reduction in the number of cells and/or cell geometry size. Additionally, the provision of discrete capacitive loads reduces the FSS susceptibility to fabrication tolerances based on placement of a fixed grid capacitance. The bandwidth increased from 1.8% to 7.3% for a total antenna thickness of approx. lambda/22, and from 1.5% to 9.2% for a thickness of approx. lambda/40. The total antenna area for each case was reduced by 55% and 12%, respectively.

Cure, David↗
NASA NTRS2007

Electrically Small Folded Slot Antenna Utilizing Capacitive Loaded Slot Lines

This paper presents an electrically small, coplanar waveguide fed, folded slot antenna that uses capacitive loading. Several antennas are fabricated with and without capacitive loading to demonstrate the ability of this design approach to reduce the resonant frequency of the antenna, which is analogous to reducing the antenna size. The antennas are fabricated on Cu-clad Rogers Duriod(TM) 6006 with multilayer chip capacitors to load the antennas. Simulated and measured results show close agreement, thus, validating the approach. The electrically small antennas have a measured return loss greater than 15 dB and a gain of 5.4, 5.6, and 2.7 dBi at 4.3, 3.95, and 3.65 GHz, respectively.

Scardelletti, Maximilian C.↗
NASA NTRS2001

Miniaturized Wilkinson Power Dividers Utilizing Capacitive Loading

This letter reports the miniaturization of a planar Wilkinson power divider by capacitive loading of the quarter wave transmission lines employed in conventional Wilkinson power dividers. Reduction of the transmission line segments from lambda/4 to between lambda/5 and lambda/12 are reported here. The input and output lines at the three ports and the lines comprising the divider itself are coplanar waveguide (CPW) and asymmetric coplanar stripline (ACPS), respectively. The 10 GHZ power dividers are fabricated on high resistivity silicon (HRS) and alumina wafers. These miniaturized dividers are 74% smaller than conventional Wilkinson power dividers, and have a return loss better than +30 dB and an insertion loss less than 0.55 dB. Design equations and a discussion about the effect of parasitic reactance on the isolation are presented for the first time.

Scardelletti, Maximilian C.↗
NASA NTRS1979

Improved driver for capacitive loads

Bias resistors with large voltage swings are replaced by transistorized current sources and bias currents are reduced to level where beta of devices is accceptable. Innovation has other applications in circuits driving pulsed capacitive loads.

Matsumoto, R. T.↗
NASA NTRS2008

High-Voltage, Asymmetric-Waveform Generator

The shapes of waveforms generated by commercially available analytical separation devices, such as some types of mass spectrometers and differential mobility spectrometers are, in general, inadequate and result in resolution degradation in output spectra. A waveform generator was designed that would be able to circumvent these shortcomings. It is capable of generating an asymmetric waveform, having a peak amplitude as large as 2 kV and frequency of several megahertz, which can be applied to a capacitive load. In the original intended application, the capacitive load would consist of the drift plates in a differential-mobility spectrometer. The main advantage to be gained by developing the proposed generator is that the shape of the waveform is made nearly optimum for various analytical devices requiring asymmetric-waveform such as differential-mobility spectrometers. In addition, this waveform generator could easily be adjusted to modify the waveform in accordance with changed operational requirements for differential-mobility spectrometers. The capacitive nature of the load is an important consideration in the design of the proposed waveform generator. For example, the design provision for shaping the output waveform is based partly on the principle that (1) the potential (V) on a capacitor is given by V=q/C, where C is the capacitance and q is the charge stored in the capacitor; and, hence (2) the rate of increase or decrease of the potential is similarly proportional to the charging or discharging current. The proposed waveform generator would comprise four functional blocks: a sine-wave generator, a buffer, a voltage shifter, and a high-voltage switch (see Figure 1). The sine-wave generator would include a pair of operational amplifiers in a feedback configuration, the parameters of which would be chosen to obtain a sinusoidal timing signal of the desired frequency. The buffer would introduce a slight delay (approximately equal to 20 ns) but would otherwise leave the fundamental timing signal unchanged. The buffered timing signal would be fed as input to the level shifter. The output of the level shifter would serve as a timing and control signal for the high-voltage switch, causing the switch to alternately be (1) opened, allowing the capacitive load to be charged from a high-voltage DC power supply; then (2) closed to discharge the capacitive load to ground. Hence, the output waveform would closely approximate a series of exponential charging and discharging curves (see Figure 2).

Beegle, Luther W.↗
NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗
NASA NTRS2010

Tunable Reduced Size Planar Folded Slot Antenna Utilizing Varactor Diodes

A tunable folded slot antenna that utilizes varactor diodes is presented. The antenna is fabricated on Rogers 6006 Duriod with a dielectric constant and thickness of 6.15 and 635 m, respectively. A copper cladding layer of 17 m defines the antenna on the top side (no ground on backside). The antenna is fed with a CPW 50 (Omega) feed line, has a center frequency of 3 GHz, and incorporates Micrometrics microwave hyper-abrupt 500MHV varactors to tune the resonant frequency. The varactors have a capacitance range of 2.52 pF at 0 V to 0.4 pF at 20 V; they are placed across the radiating slot of the antenna. The tunable 10 dB bandwidth of the 3 GHz antenna is 150 MHz. The varactors also reduce the size of the antenna by 30% by capacitively loading the resonating slot line. At the center frequency, 3 GHz, the antenna has a measured return loss of 44 dB and a gain of 1.6 dBi. Full-wave electromagnetic simulations using HFSS are presented that validate the measured data. Index Terms capacitive loading, Duriod, folded slot antenna, varactor.

Scardelletti, Maximilian C.↗
DOE OSTI2021

Spread Spectrum Time Domain Reflectometry and Steepest Descent Inversion to Measure Complex Impedance

In this paper, we present a method for estimating complex impedances using reflectometry and a modified steepest descent inversion algorithm. We simulate spread spectrum time domain reflectometry (SSTDR), which can measure complex impedances on energized systems for an experimental setup with resistive and capacitive loads. A parametric function, which includes both a misfit function and stabilizer function, is created. The misfit function is a least squares estimate of how close the model data matches observed data. The stabilizer function prevents the steepest descent algorithm from becoming unstable and diverging. Steepest descent iteratively identifies the model parameters that minimize the parametric function. We validate the algorithm by correctly identifying the model parameters (capacitance and resistance) associated with simulated SSTDR data, with added 3 dB white Gaussian noise. With the stabilizer function, the steepest descent algorithm estimates of the model parameters are bounded within a specified range. Furthermore, the errors for capacitance (220pF to 820pF) and resistance (50 Ω to 270 Ω) are < 10%, corresponding to a complex impedance magnitude |R +1/jωC| of 53 Ω to 510 Ω.

14 SOLAR ENERGY↗
NASA NTRS1992

Low power, highly linear output buffer

A class AB CMOS output buffer has been designed for use on an IR focal plane array. Given the requirements for power dissipation and load capacitance a class A output, such as a source follower, would be unsuitable. The approach taken uses a class AB amplifier configured as a charge integrator. Thus it converts a charge packet in the focal plane multiplexer to a voltage which is then the output of the focal plane. With a quiescent current of 18 micro-a and a load capacitance of 100 pf, the amplifier has an open loop unity gain bandwidth of 900 khz. Integral nonlinearity is better than .03 percent over 5.5 volts when run with VDD-VSS = 6v.

Foley, D.↗
NASA NTRS1989

Radiation dependence of inverter propagation delay from timing sampler measurements

A timing sampler consisting of 14 four-stage inverter-pair chains with different load capacitances was fabricated in 1.6-micron n-well CMOS and irradiated with cobalt-60 at 10 rad(Si)/s. For this CMOS process the measured results indicate that the rising delay increases by about 2.2 ns/Mrad(Si) and the falling delay increase is very small, i.e., less than 300 ps/Mrad(Si). The amount of radiation-induced delay depends on the size of the load capacitance. The maximum value observed for this effect was 5.65 ns/pF-Mrad(Si). Using a sensitivity analysis, the sensitivity of the rising delay to radiation can be explained by a simple timing model and the radiation sensitivity of dc MOSFET parameters. This same approach could not explain the insensitivity of the falling delay to radiation. This may be due to a failure of the timing model and/or trapping effects.

Buehler, M. G.↗
NASA NTRS1975

An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.

Lin, H. C.↗
NASA NTRS2016

Thermal Vacuum Test Correlation of A Zero Propellant Load Case Thermal Capacitance Propellant Gauging Analytics Model

This thesis describes the development and test data validation of the thermal model that is the foundation of a thermal capacitance spacecraft propellant load estimator. Specific details of creating the thermal model for the diaphragm propellant tank used on NASA's Magnetospheric Multiscale spacecraft using ANSYS and the correlation process implemented to validate the model are presented. The thermal model was correlated to within plus or minus 3 degrees Centigrade of the thermal vacuum test data, and was found to be relatively insensitive to uncertainties in applied heat flux and mass knowledge of the tank. More work is needed, however, to refine the thermal model to further improve temperature predictions in the upper hemisphere of the propellant tank. Temperatures predictions in this portion were found to be 2-2.5 degrees Centigrade lower than the test data. A road map to apply the model to predict propellant loads on the actual MMS spacecraft toward its end of life in 2017-2018 is also presented.

Thermal↗
NASA NTRS2016

Thermal Vacuum Test Correlation of a Zero Propellant Load Case Thermal Capacitance Propellant Gauging Analytical Model

This thesis describes the development and correlation of a thermal model that forms the foundation of a thermal capacitance spacecraft propellant load estimator. Specific details of creating the thermal model for the diaphragm propellant tank used on NASA's Magnetospheric Multiscale spacecraft using ANSYS and the correlation process implemented are presented. The thermal model was correlated to within plus or minus 3 degrees Celsius of the thermal vacuum test data, and was determined sufficient to make future propellant predictions on MMS. The model was also found to be relatively sensitive to uncertainties in applied heat flux and mass knowledge of the tank. More work is needed to improve temperature predictions in the upper hemisphere of the propellant tank where predictions were found to be 2 to 2.5 C lower than the test data. A road map for applying the model to predict propellant loads on the actual MMS spacecraft toward its end of life in 2017-2018 is also presented.

Gauging↗
NASA NTRS2007

Development of a Tunable Electromechanical Acoustic Liner for Engine Nacelles

This report describes the development of a tunable electromechanical Helmholtz resonator (EMHR) for engine nacelles using smart materials technology. This effort addresses both near-term and long-term goals for tunable electromechanical acoustic liner technology for the Quiet Aircraft Technology (QAT) Program. Analytical models, i.e. lumped element model (LEM) and transfer matrix (TM) representation of the EMHR, have been developed to predict the acoustic behavior of the EMHR. The models have been implemented in a MATLAB program and used to compare with measurement results. Moreover, the prediction performance of models is further improved with the aid of parameter extraction of the piezoelectric backplate. The EMHR has been experimentally investigated using standard two-microphone method (TMM). The measurement results validated both the LEM and TM models of the EMHR. Good agreement between predicted and measured impedance is obtained. Short- and open circuit loads define the limits of the tuning range using resistive and capacitive loads. There is approximately a 9% tuning limit under these conditions for the non-optimized resonator configuration studied. Inductive shunt loads result in a 3 degree-of-freedom DOF) system and an enhanced tuning range of over 20% that is not restricted by the short- and open-circuit limits. Damping coefficient ' measurements for piezoelectric backplates in a vacuum chamber are also performed and indicate that the damping is dominated by the structural damping losses, such as compliant boundaries, and other intrinsic loss mechanisms. Based on models of the EMHR, a Pareto optimization design of the EMHR has been performed for the EMHR with non-inductive loads. The EMHR with non-inductive loads is a 2DOF system with two resonant fiequencies. The tuning ranges of the two resonant frequencies of the EMHR with non-inductive loads cannot be optimized simultaneously; a trade-off (i.e., a Pareto solution) must be reached. The Pareto solution provides the information for a designer that shows how design trade-offs can be used to satisfy specific design requirements. The optimization design of the EMHR with inductive loads aims at optimal tuning of these three resonant fiequencies. The results indicate that it is possible to keep the acoustic reactance of the resonator close to a constant over a given frequency range. An effort to mimic the second layer of the NASA 2DOF liner using a piezoelectric composite diaphragm has been made. The optimal acoustic reactance of the second layer of the NASA 2DOF liner is achieved using a thin PVDF composite diaphragm, but matching the acoustic resistance requires further investigation. Acoustic energy harvesting is achieved by connecting the EMHR to an energy reclamation circuit that converts the ac voltage signal across the piezoceramic to a conditioned dc signal. Energy harvesting experiment yields 16 m W continuous power for an incident SPL of 153 dB. Such a level is sufficient to power a variety of low power electronic devices. Finally, technology transfer has been achieved by converting the original NASA ZKTL FORTRAN code to a MATLAB code while incorporating the models of the EMHR. Initial studies indicate that the EMHR is a promising technology that may enable lowpower, light weight, tunable engine nacelle liners. This technology, however, is very immature, and additional developments are required. Recommendations for future work include testing of sample EMHR liner designs in NASA Langley s normal incidence dual-waveguide and the grazing-incidence flow facility to evaluating both the impedance characteristics as well as the energy reclamation abilities. Additional design work is required for more complex tuning circuits with greater performance. Poor electromechanical coupling limited the electromechanical tuning capabilities of the proof of concept EMHR. Different materials than those studies and perhaps novel composite material systems may dramatically improvehe electromechanical coupling. Such improvements are essential to improved mimicking of existing double layer liners.

Liu, Fei↗
NASA NTRS2016

Single-Event Latchup Testing of the Micrel MIC4424 Dual Power MOSFET Driver

We conducted 47 exposures of four different MIC4424 devices and did not observe any SEL or high-current events. This included worst-case conditions with a LET of 81 MeV-sq cm/mg, applied voltage of 18.5 V, a case temperature greater than 120 C, and a final fluence of 1x10(exp 7)/sq cm. We also monitored both the outputs for the presence of SETs. While the period of the 1 MHz square wave was slightly altered in some cases, no pulses were added or deleted. 1. Purpose: The purpose of this testing is to characterize the BiCMOS/DMOS Micrel MIC4424 dual, non-inverting MOSFET driver for single-event latchup (SEL) susceptibility. These data will be used for flight lot evaluation purposes. 2. Devices Tested: The MIC4423/4424/4425 family are highly reliable BiCMOS/DMOS buffer/driver MOSFET drivers. They are higher output current versions of the MIC4426/4427/4428. They can survive up to 5V of noise spiking, of either polarity, on the ground pin. They can accept, without either damage or logic upset, up to half an amp of reverse current (either polarity) forced back into their outputs. Primarily intended for driving power MOSFETs, the MIC4423/4424/4425 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak currents, and fast switching times. Heavily loaded clock lines, coaxial cables, or piezoelectric transducers are some examples. The only known limitation on loading is that total power dissipated in the driver must be kept within the maximum power dissipation limits of the package. Five (5) parts were provided for SEL testing. We prepared four parts for irradiation and reserved one piece as an un-irradiated control. More information about the devices can be found in Table 1. The parts were prepared for testing by removing the lid from the CDIP package to expose the target die. The parts were then soldered to small copper circuit adapter boards for easy handling. These parts are fabricated in a bulk BiCMOS/DMOS technology. Since we do not know the number of overlayers used in the fabrication processes, linear energy transfer calculations are determined based on the top-surface incident ion species and kinetic energy.

Power MOSFET↗