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Results for “capacitor sizing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Analytical Expression for DC Link Capacitor Current in a Cascaded H-Bridge Multi-Level Active Front-End Converter

Medium-voltage grid-tied systems often use a cascaded H-bridge multi-level active front-end. In this converter, dc link bus capacitors play an important role in stabilizing the converter and enabling both active and reactive power injections. The present work provides analytical expressions for the capacitor current, which are essential for optimizing system design (especially capacitor size vs. lifetime). Then, the expression is incorporated into the grid connected bidirectional power system model. Consequently, this work contributes to the guiding principles to choose accurate dc link capacitor ratings against grid-side power delivery requirements. The analytical results have been validated with detailed simulations and hardware results.

cascaded H-bridge, carrier-based PWM, dc-link capa↗
DOE OSTI2024

Stability Considerations for Virtual Capacitor Control in Constant Power DC Loads

In a DC grid, constant power loads (CPLs) necessitate a large bus capacitor to prevent negative impedance instability. Some of the capacitance can be realized virtually through CPL control to reduce the bus capacitor size. Here, this paper analytically studies system stability with virtual capacitor control. We demonstrate that the effectiveness of virtual capacitor control is highly sensitive to the implementation of the derivative action required to emulate the capacitor. For the first time, we theoretically demonstrate that a virtual capacitor can stabilize the system without any physical bus capacitor, provided that a set of analytically derived conditions are met. However, this stabilization is not achievable in practice due to the influence of non-idealities. In an example system requiring a $14$ mF capacitor to stably support the CPL, we show that stability can be achieved through virtual capacitor control, using only a 2 mF physical capacitor to account for the switching ripple non-idealities. Hardware-in-the-loop tests verify the analysis.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Analysis and design of DC-link capacitor in cascaded H-bridge multilevel active front-end converter

Medium-voltage grid-tied systems often use a cascaded H-bridge multi-level active front-end. In this converter, dc link bus capacitors play an important role in stabilizing the converter and enabling both active and reactive power injections. The present work provides analytical expressions for the capacitor current, which are essential for optimizing system design (especially capacitor size vs. lifetime). Then, the expression is incorporated into the grid connected bidirectional power system model. Consequently, this work contributes to the guiding principles to choose accurate dc link capacitor ratings against grid-side power delivery requirements. DC-link capacitors come with an expiration date which is dependent on the operating power and voltage values. Lack of information about the lifetime of the dc-link capacitor creates uncertainty in the duration of online operation of the converter, thus increasing the probability of a contingency outage. The lifetime of the capacitor can range from only a few seconds of online operation of the station due to under-sizing, to a compromised quality of power flowing through other solid state devices which may not have been designed for the transients that are caused by over-sizing of the dc-link capacitor. A better estimate of the lifetime of these capacitors can help maximize usage and maintain scheduled outages more efficiently, without disruption in service.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

7.2 kV Three-Port SiC Single-Stage Current-Source Solid-State Transformer With 90 kV Lightning Protection

This article proposes a multiport modular single-stage current-source solid-state transformer (SST) for applications like photovoltaic, energy storage integration, electric vehicle fast charging, data center, etc. The 7.2 kV 50 kVA current-source SST consists of five input-series output-parallel modules, each based on 3.3 kV SiC reverse-blocking MOSFET-plus-diode modules. The proposed SST has some unique features. First, compared to the voltage-source or matrix converter-based SSTs, the current-source SST has a unique advantage of single-stage isolated AC/DC or AC/AC conversion with an inductive DC link, but no medium-voltage (MV) AC experiments have been reported. This article for the first time demonstrates MV AC current-source SST up to 7.5 kV peak. Second, the multiport SST has a buffer port for active power decoupling (APD) or energy storage integration. The double-line-frequency power ripple from single-phase AC grid normally results in a large capacitor size in MV SSTs. The APD scheme is proposed in MV applications for the first time to enable a reduced DC link and the electrolytic capacitor-less SST with high reliability. Third, as a direct grid-connected converter without line-frequency transformer, insulation and protection are critical. A medium-frequency transformer design passes 55 kV basic-insulation level (BIL) and 60 kV high potential dielectrics withstand test with only 0.09% leakage inductance. Importantly, a lightning protection scheme is presented to protect the SST itself from 90 kV BIL impulse. Fourth, the proposed current-source SST topology is a modular soft-switching solid-state transformer (M-S4T) with full-range zero-voltage switching and controlled dv/dt for low electromagnetic interference. Furthermore, these concepts are verified in a three-port M-S4T prototype with forced oil cooling under single-module, stacked-module, steady-state, and dynamic operations.

14 SOLAR ENERGY↗
DOE OSTI2021

A Bulk-Capacitance Reduction Method Using Self-Driven Thyristor for AC-DC Converters

Universal serial bus power delivery (USB-PD) fast chargers equipped with wide-bandgap devices are driven to higher power density and efficiency. Furthermore, the indispensable high-voltage bulk capacitors used to smooth the rectifier output could take 40% of the total system volume due to the large capacitance value required. This paper discussed a capacitor reduction method using a self-driven thyristor scheme comprised of only three components in total. No extra control circuit is needed. Circuit analysis and design equations are presented, and the design results are implemented in a 60-W GaN-based active-clamp flyback converter. The measurement results on the prototype show a 36.4% reduction of the bulk-capacitor size with similar efficiency compared to the conventional solution.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2025

DC-Link Capacitor Design for a Neutral-Point-Less Three-Level Dual-Phase Inverter for Traction Application

Conventional multilevel inverters, such as neutral￾point-clamped and T-type inverters, have gained popularity in electric vehicle applications due to their advantages, including high voltage range, high power capability, low switching losses, low total harmonic distortion, and low electromagnetic interference. However, these traditional multilevel inverters require a neutral point connection to generate a zero-voltage vector. The neutral point current oscillates at three times the fundamental frequency, leading to voltage imbalance and overvoltage stress on the power modules. Additionally, the use of two stacked DC-link capacitors increases the volume required for the same overall capacitance and complicates packaging due to ripple current and heat dissipation from separate components. This is a significant concern for traction drive units, where space is limited. In this paper, a neutral-point-less multilevel dual three￾phase inverter topology is investigated for traction inverter applications. Simulation results demonstrate that the proposed topology effectively retains the benefits of multilevel operation while utilizing a single DC-link capacitor. The inverter model was simulated in conjunction with an industry-standard battery model to evaluate the potential for capacitor size reduction compared to a conventional three-level inverter.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2026

Exploding Bridgewire (EBW) Detonators: An Example of Synergistic Multiphysics

Exploding bridgewire (EBW) detonators are highly temporally reproducible explosive devices that require the rapid discharge of a high‐voltage capacitance to operate and so are immune to most of the accidental hazards associated with traditional electric detonators. They have been demonstrated to be safe enough for use in high‐consequence explosive applications. Despite continued use for over 82 years, understanding the exact mechanism of operation has remained elusive. Various researchers have ascribed either deflagration‐to‐detonation (DDT) or shock‐to‐detonation (SDT) phenomena observed in other explosive events to explain the science behind the successful engineering; however, a rigorous justification has been absent. Previously, we have demonstrated a complex interaction in EBW detonators between large electrical currents, non‐equilibrium thermodynamic material states, plasma physics, powder compaction phenomena, shock physics, photochemistry, and rapid conventional explosive chemical reaction processes. Specifically, we have made progress in understanding the complex multiphysics that operates in these detonators and demonstrating that it is a serendipitous synergy between UV light emitted from the arc formed as the bridge is electrically exploded and the accompanying short‐duration shock transmitted into the explosive powder bed that allows these devices to function at practical capacitor sizes and charge voltages. This insight not only places the topic on a firmer scientific footing but potentially enables new approaches to safe detonator design.

36 MATERIALS SCIENCE↗
DOE OSTI2020

DC Link Capacitor Reduction with Feedforward Control in Series-Series Compensated Wireless Power Transfer Systems

This paper presents the use of feedforward control to reduce the input side DC link capacitance of series-series compensated wireless power transfer (WPT) systems. Compared to conventional control schemes for WPT systems, the proposed feedforward-based approach achieves significant reduction in the DC link capacitor without any complicated voltage or current sensing requirements from the secondary side. This results in more compact hardware architecture. The proposed method shows minimal increase in the turn-on switching loss of the inverter. The switching loss is analyzed, and detailed results are presented relating the switching loss to the DC link capacitance and voltage ripple for proper tradeoff between losses and capacitor size. Simulation and experimental results presented validate the proposed scheme.

Mukherjee, Subho↗
DOE OSTI2020

Capacitor Voltage Ripple Estimation and Optimal Sizing of Modular Multi-Level Converters for Variable-Speed Drives

This article deals with the sizing of submodule capacitors for modular multilevel converters (MMCs) used for variable speed drives for medium voltage and high voltage electric machines. Variable speed drives are required to run over a wide frequency range from zero to a few hundred Hz or even over 1 kHz. Under low frequency operation (<30 Hz), a large current ripple flowing through the MMC submodule capacitors will cause significant capacitor voltage fluctuation. This article proposes an optimal submodule capacitor selection method based on the common-mode voltage injection. The proposed sizing model includes two functions: 1) accurately estimating the capacitor voltage ripple based on the drive system parameters; and 2) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and experimental results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

42 ENGINEERING↗
DOE OSTI2023

On the Interplay between Size and Disorder in Suppressing Intercalation-Induced Phase Transitions in Pseudocapacitive Nanostructured MoS 2

Pseudocapacitors are an emerging class of energy storage materials that offer an attractive compromise between the energy density of batteries and power density of electric double-layer capacitors. Decreasing particle size and increasing surface area of battery materials is a common approach for introducing pseudocapacitive behavior and increasing power density. However, in many cases, as the crystal size is reduced, lattice disorder of unknown extent is also introduced, making it difficult to characterize the relative contribution of size and disorder to fast-charging performance. Here, in this work, a series of nanostructured MoS 2 materials are synthesized with different crystallite sizes and degrees of crystallinity to decouple the effects of size and disorder on charge/discharge kinetics. The extent and type of disorder in each material is quantified by total X-ray scattering experiments and pair distribution function analyses. Electrochemical characterization, including galvanostatic rate capability, cyclic voltammetry, and various kinetic analyses, are used to demonstrate that both decreasing particle size and introducing lattice disorder are effective strategies for increasing charge storage kinetics, and that the effects are additive. Finally, operando X-ray diffraction measurements show that both size and disorder can be used suppress first-order Li + intercalation-induced phase transitions, a key feature for enabling pseudocapacitive charge storage.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Hybrid MEMS-CMOS ion traps for NISQ computing

Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. Finally, we also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Investigation into the crystal structure–dielectric property correlation in barium titanate nanocrystals of different sizes

For high capacitance multilayer ceramic capacitors, high dielectric constant and lead-free ceramic nanoparticles are highly desired. However, as the particle size decreases to a few tens of nanometers, their dielectric constant significantly decreases, and the underlying mechanism has yet to be fully elucidated. Herein, we report a systematic investigation into the crystal structure–dielectric property relationship of combustion-made BaTiO 3 (BTO) nanocrystals. When the nanocrystal size was 100 nm and below, a metastable paraelectric cubic phase was found in the as-received BTO (denoted as arBTO) nanocrystals based on an X-ray diffraction (XRD) study. A stable ferroelectric tetragonal phase was present when the nanocrystal size was above 200 nm. Notably, the cubic arBTO (particle size ≤100 nm) exhibited tetragonal fluctuations as revealed by Raman spectroscopy, whereas the tetragonal arBTO (particle size ≥200 nm) contained ~10% cubic fraction according to the Rietveld fitting of the XRD profiles. Thermal annealing of the multi-grain tetragonal arBTO at 950 °C yielded single crystals of annealed BTO (denoted as anBTO), whose dielectric constants were higher than those of arBTO. However, the single crystalline anBTO prevented the formation of 90° domains; therefore, they exhibited a low dielectric constant of ~300. Although X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy could not identify the exact structural defects, our study revealed that surface and bulk defects formed during synthesis affect the final crystal structures and thus the dielectric properties of BTO nanocrystals with different sizes. Finally, the understanding obtained from this study will help us design high dielectric constant perovskite nanocrystals for next-generation multilayer ceramic capacitor applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Thermal Analysis of a Polypropylene Capacitor for Resonant Tuning Networks in WPT Applications

This study presents the thermal analysis of polypropylene capacitors operating at high frequencies and high currents used in the resonant tuning networks for electric vehicle (EV) wireless charging systems. The thermal analysis and performance results of the CELEM polypropylene capacitors are presented at different currents for a polyphase wireless power transfer (WPT) system while the study can be expanded to other capacitors by different manufacturers. Thermal equivalent circuit of the capacitor is derived and required cold plate size and design calculations are conducted by modeling the polypropene capacitor in MATLAB. The polypropene capacitor's finite element analysis (FEA) model is developed using COMSOL Multiphysics simulation software, and the thermal characteristics and analysis of the capacitor are presented in this paper.

Aktas, Ahmet↗
DOE OSTI2025

Coexisting Phases in NaNbO 3 Thin Films Influenced by Epitaxial Strain and Size Effects

Coherently strained NaNbO 3 thin films are synthesized across a range of thicknesses, enabling the study of size effects under epitaxial strain in antiferroelectric thin films without relaxation. Competing antiferroelectric‐ferroelectric phases are observed, leading to the stabilization of phase coexistence, multistate switching with strong retention and fatigue performance, and potential avenues to boost energy storage properties.

antiferroelectrics↗
DOE OSTI2022

Surface Functionalized Barium Titanate Nanoparticles: A Combined Experimental and Computational Study

Barium titanate (BTO) nanoparticles show great potential for use in electrostatic capacitors with high energy density. This includes both polymer composite and sintered capacitors. However, questions about the nanoparticles' size distribution, amount of agglomeration, and surface ligand effect on performance properties remain. Reducing particle agglomeration is a crucial step to understanding the properties of nanoscale particles, as agglomeration has significant effects on the composite dielectric constant. BTO surface functionalization using phosphonic acids is known reduce BTO nanoparticle agglomeration. We explore solution synthesized 10 nm BTO particles with tert-butylphosphonic acid ligands. Recent methods to quantifying agglomeration using an epoxy matrix before imaging shows that tert-butylphosphonic acid ligands reduce BTO agglomeration by 33%. Thermometric, spectroscopic, and computational methods provide confirmation of ligand binding and provide evidence of multiple ligand binding modes on the BTO particle surface.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Extreme Efficiency 240 Vac to Load Data Center Power Delivery Topologies and Control

The research explored innovative new circuit topologies and power converter architectures for data center power delivery, from the 240 V ac voltage at the input of a server rack, down to the less than 1 V dc power supply of the latest microprocessors. The research pursued three parallel tracks to increase the power conversion efficiency and to reduce the overall size of the servers: 1) An innovative new ac-dc power converter topology which enables improved efficiency through use of a novel direct step-down topology, well suited for the popular 48V dc power distribution. 2) A new series-stacked power delivery approach for servers comprising a large number of similar loads, such as hard drives in storage servers. The approach greatly reduces the power conversion losses, and achieves efficiency well over 99%. 3) A new family of hybrid switched-capacitor power converters that enable improved efficiency and reduced size through the use of dense ceramic capacitors and new circuit topologies that leverage GaN and low-voltage Si transistor technology. Together, the accomplished research achieved the goal of reducing the power conversion losses in datacenters, thereby reducing greenhouse gas emissions, operating costs, and overall electricity consumption.

24 POWER TRANSMISSION AND DISTRIBUTION↗