Designers manual for circuit design by analog/digital techniques Final report
Manual for designing circuits by hybrid computer
Beck, C. H.↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Statistical circuit design for yield improvement in CMOS circuits
This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.
Kamath, H. J.↗
Adaptability of FET models to computer-aided circuit design Final report
Equivalent circuit and modified and approximate models for metal oxide semiconductor-field effect transistor devices, and adaptability to computerized circuit design
Birznieks, U.↗
Iterative optimization techniques for circuit design
Iterative optimization techniques for circuit design
OPTIMIZATION↗
A Parallel Genetic Algorithm for Automated Electronic Circuit Design
We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.
Lohn, Jason D.↗
Computer-Aided Circuit Design Seminar
Computer-aided circuit design - network analysis methods, options, parameters, programs, filters, sensitivity, and engineering
CONFERENCE↗
CIRCAL - On-line circuit design.
On-line nonlinear circuit design, discussing computer program for evaluating performance resulting from modifications
COMPUTER METHOD↗
An introduction to on-line circuit design.
On-line computerized circuit design, discussing network theory, linguistics, numerical analysis and programming systems
Dertouzos, M. L.↗
Self-checking sequential circuit design using m-out-of-n codes
A technique for designing sequential circuits which are totally self-checking for single stuck at faults is presented. This technique uses m-out-of-n codes for state assignments and for output encoding. The next stage logic and the output logic are implemented such that any stuck-at-fault will either create a single bit error or unidirectional multibit error at the output. The technique has been applied to MCNC benchmark circuits and the overhead is estimated.
Busaba, F. Y.↗
On-line circuit design - An introduction.
On-line circuit design reflecting interrelation and relevance of network theory, linguistics, numerical analysis, programming and on-line computation
Dertouzos, M. L.↗
Man-machine interactive system simplifies computer-aided circuit design
Langley interactive computerized circuit analysis capability /LICCA/ enables designer to draw electronic circuit diagrams on cathode ray tube screen. This information is submitted as input to user-selected circuit analysis program. LICCA accommodates binary logic circuits and circuits with discrete components, and monitors operator's instructions to detect errors.
Bavuso, S. J.↗
Computer aids for worst case electronic circuit design
Computer aids for worst case electronic circuit design
DIGITAL COMPUTER↗
A Parallel Genetic Algorithm for Automated Electronic Circuit Design
Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.
Long, Jason D.↗
CIRCAL-2 - General-purpose on-line circuit design.
CIRCAL-2 is a second-generation general-purpose on-line circuit-design program with the following main features: (1) multiple-analysis capability; (2) uniform and general data structures for handling text editing, network representations, and output results, regardless of analysis; (3) special techniques and structures for minimizing and controlling user-program interaction; (4) use of functionals for the description of hysteresis and heat effects; and (5) ability to define optimization procedures that 'replace' the user. The paper discusses the organization of CIRCAL-2, the aforementioned main features, and their consequences, such as a set of network elements and models general enough for most analyses and a set of functions tailored to circuit-design requirements. The presentation is descriptive, concentrating on conceptual rather than on program implementation details.
Dertouzos, M. L.↗
Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration
Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.
digital circuits designs↗
Foundations of computer-aided circuit design by singular imbedding
Computer-aided circuit design by imbedding singular elements to transform network synthesis into analysis problem
Kozemchak, E. B.↗
Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications
Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.
Michael J Krasowski↗
Computer-aided linear-circuit design.
Usually computer-aided design (CAD) refers to programs that analyze circuits conceived by the circuit designer. Among the services such programs should perform are direct network synthesis, analysis, optimization of network parameters, formatting, storage of miscellaneous data, and related calculations. The program should be embedded in a general-purpose conversational language such as BASIC, JOSS, or APL. Such a program is MARTHA, a general-purpose linear-circuit analyzer embedded in APL.
Penfield, P.↗