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Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
The resiliency offered by a microgrid may be lost if the microgrid is not properly protected during short-circuit faults inside its boundaries. Many studies conclude that protecting microgrids in islanded mode is very challenging due to the limited short-circuit capability of distributed energy resources (DERs). The limited short-circuit capability of DERs typically inhibits the use of reliable and affordable overcurrent protective devices in microgrids. Although extensive research on microgrid protection is available in the literature, to date this research has not led to a cost-effective, commercially available relay that effectively tackles the challenges of microgrid protection. This work proposes hardware modifications to enhance the current contribution of an energy storage inverter with the objective of enabling the use of legacy overcurrent protection for islanded microgrids. This paper demonstrates through experimental results that few modifications are required in the inverter to significantly enhance its current contribution. In this study, a three-phase energy storage inverter was modified to provide three times its rated current during three-phase faults, which proved sufficient current for enough time to enable fuse-relay, and relay-to-relay coordination. The proposed modifications effectively increase the current contribution of the inverter, which is a promising advancement to allow the adoption of overcurrent protective devices for protecting microgrids.
A fault injector system, called an in-circuit injector, was designed and developed to facilitate fault injection experiments performed at NASA-Langley's Avionics Integration Research Lab (AIRLAB). The in-circuit fault injector (ICFI) allows fault injections to be performed on electronic systems without special test features, e.g., sockets. The system supports stuck-at-zero, stuck-at-one, and transient fault models. The ICFI system is interfaced to a VAX-11/750 minicomputer. An interface program has been developed in the VAX. The computer code required to access the interface program is presented. Also presented is the connection procedure to be followed to connect the ICFI system to a circuit under test and the ICFI front panel controls which allow manual control of fault injections.
Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.
The internetworking of grid-connected power electronics converters (PECs) in photovoltaic (PV) farms has inevitably expanded the cyber-attack surfaces. Here this paper presents a comprehensive study on cyber-attack detection and diagnosis for PEC-enabled PV farms via single waveform sensor to distinguish between normal conditions, open-circuit faults, short-circuit faults, and cyber-attacks. To our knowledge, this has not been attempted before. Firstly, we propose frequency-domain magnitude-based residuals to identify short-circuit faults and a time-domain mean current vector-based feature to distinguish open-circuit faults from other threats. These features can fully reflect the specific physical characteristics of PV farms during threat duration. Secondly, unlike micro phasor measurement units (µPMU) and raw electric waveform-based methods, the proposed innovative features can address novel cyber-attacks that are excluded from the training process. Thirdly, an online hardware-in-the-loop (HIL) testbed using the OPAL-RT real-time digital simulator has verified the effectiveness. The monitoring system runs in real-time while using HIL as an operational solar farm and a National Instruments (NI) data acquisition card as the electric waveform sensor at the point of coupling.
An investigation was undertaken to make the elctrocardiography (ECG) and the electromyography (EMG) signal conditioning circuits two-fault tolerant and to update the circuitry. The present signal conditioning circuits provide at least one level of subject protection against electrical shock hazard but at a level of 100 micro-A (for voltages of up to 200 V). However, it is necessary to provide catastrophic fault tolerance protection for the astronauts and to provide protection at a current level of less that 100 micro-A. For this study, protection at the 10 micro-A level was sought. This is the generally accepted value below which no possibility of microshock exists. Only the possibility of macroshock exists in the case of the signal conditioners. However, this extra amount of protection is desirable. The initial part deals with current limiter circuits followed by an investigation into the signal conditioner specifications and circuit design.
This final report describes the methods and results of applying Spread Spectrum Time Domain Reflectivity (SSTDR) for String Monitoring in PV Power Plants for DE-EE0008169. The project created a new system for both detecting and locating electrical faults in photovoltaic systems. In this work, we address photovoltaic electric faults that are both common and costly. Based on interviews with photovoltaic power plant owners, operators, and maintainers, three types of faults are common and of significant interest: disconnects, ground faults, and arc faults. Disconnects can originate from many sources. They are often due to everyday events, such as lawnmowing (accidentally running over a cable), animals eating through the cables, or degradation that occurs over time due to corrosion or general degradation. Ground faults occur when the cables (for example, due to frayed insolation) connect to the ground, relaying current into the ground. These faults are particularly problematic since the ground faults are often intermittent. That is, ground faults commonly appear during rain storms due to a change in soil conductivity and then disappear when the rain ends. This makes the ground fault difficult to find because while current systems can detect the overall change in voltage and current associated with a ground fault, technicians are necessary to locate the fault. As a result, ground faults may disappear before the technician arrives at the power plant. Hence, locating and fixing ground faults often require multiple trips. We also study arc faults, which can result when nearby conductors create an arc of electrical current through the air. While less common, arc faults can be extremely dangerous. The energetic electrical arc can cause fires and destroy equipment, costing significant damage. Overall all three types of faults cost owners and operators money, either from the destruction of equipment or from technician time. Furthermore, while devices exist for detecting ground faults (ground fault circuit interrupters) and arc faults (arc fault circuit interrupter), these systems only search patterns of electrical current that correspond to each fault. This information cannot be used to locate the fault. In addition, these protection systems experience nuisance trips due to nearby electromagnetic interference, such as from a lawn mower or other motors that produce significant amounts of electromagnetic radiation. Hence, the overall goal of this project is to create an SSTDR tool that provides photovoltaic power plants with more reliable fault detection in addition to the localization of faults. SSTDR works by transmitting electrical signals into the photovoltaic string. Those signals reflect from impedance discontinuities (i.e., disconnects, ground faults, and arc faults). These faults are then detected by measuring the presence of a reflection at the SSTDR and can be located by identifying the location of that reflection in time. In addition, unlike current protection systems, these systems do not experience nuisance trips since their low amplitude, high frequency, and coded signal can by analyzed without interference from the regular operational voltage on the photovoltaic string.
Corrective circuit prevents the appearance of erroneous output signals from the possible failure of any single-channel element interconnected in parallel binary information channels. The circuit is simplified and economical because it does not use redundant channels.
Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.
Modern societies would not survive without electricity and at the same time electrical faults could cause and have caused many catastrophes—mainly deadly fires—to our societies. There are two types of electricity sources: the voltage source such as generators, charged batteries and capacitors, and the current source such as charged inductors, current-regulated rectifiers, and superconducting magnetic energy storage. An “ideal” voltage source—that is often-sought-or-intentionally engineered—generates a constant voltage irrespective of its load current, and an “ideal” current source injects a constant current irrespective of its load voltage. However, two problems exist: (1) voltage or current sources do not represent many emerging natural/renewable energy sources such as wind turbine generators, photovoltaic cells, and fuel cells, whose output voltage and current are strongly dependent on each other, and (2) a short-circuit fault to an artificially-made and controlled “ideal” voltage source or an open-circuit fault to an “ideal” current source can cause catastrophic failures of the source itself and its surrounding circuits due to large (theoretically infinite) short-circuit current or open-circuit voltage. Here we introduce an impedance source concept to represent, characterize, and model those electricity sources whose output voltage and current are strongly dependent on each other. First, we found that many electric sources with no feedback (or active) control of their output voltage and/or current are a natural impedance source with inherent fault protection at short-circuit or open-circuit faults. Second, any electrical source can be artificially controlled to mimic a natural impedance source. Finally, we show how to apply natural impedance sources and nature-mimicking artificially-controlled sources to the electricity grid—the most complex machine ever made by human beings—to realize electricity grids that are naturally stable, self-protected against electrical faults, and resilient to natural and human-made events.
Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.
The objective of this research is to conduct various fault simulation studies for diagnosing the type and location of faults in the power distribution system. Different types of faults are simulated at different locations within the distribution system and the faulted waveforms are monitored at measurable nodes such as at the output of the DDCU's. These fault signatures are processed using feature extractors such as FFT and wavelet transforms. The extracted features are fed to a clustering based neural network for training and subsequent testing using previously unseen data. Different load models consisting of constant impedance and constant power are used for the loads. Open circuit faults and short circuit faults are studied. It is concluded from present studies that using features extracted from wavelet transforms give better success rates during ANN testing. The trained ANN's are capable of diagnosing fault types and approximate locations in the solar dynamic power distribution system.
Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.
This report presents a comparative assessment of the performance of frequency domain reflectometry (FDR) and spread spectrum time domain reflectometry (SSTDR) in detecting a wide range of electrical cable anomalies. All tests and results reported herein were performed at the PNNL Accelerated and Real-Time Environmental Nodal Assessment (ARENA) cable and motor test bed. The primary objective of this work was to evaluate the effectiveness of SSTDR, a fledgling cable monitoring technique that shows promise for application in online monitoring of energized cable systems, against FDR, an offline technique widely employed in the nuclear power plant (NPP) industry. FDR tests are becoming more widely used in nuclear power plant cable aging management and test programs – particularly for low voltage cables. FDR capabilities for these kinds of tests have been reported by PNNL and others. The FDR test is performed on de-energized cables by connecting the FDR instrument to two of the cable conductors, or one conductor and the shield. A broad band low voltage (< 5 V) chirp is introduced in the cable, and any reflected response is captured in the frequency domain. The captured reflection is then processed by performing an inverse Fourier transform to a time domain response which can then be converted to a distance response based on the cable velocity of propagation (VoP). SSTDR measurements are functionally similar to FDR measurements in that a broad-band voltage signal composed of a square or sine wave modulated pseudo-random sequence of chips (< 5 volts), is injected onto one of the cable conductors. The injected signal will experience partial energy reflection and transmission at each impedance discontinuity along the transmission line. Any reflected response is detected by computing a cross-correlation between the reflected signals and a delayed copy of the incident SSTDR signal. the time delay for the reflected signal to experience the best matched correlation with the incident signal, indicates the travel time for the signal to reach a change in impedance. By knowing this time delay and velocity of propagation (VoP) of the signal, one can compute the physical distance. A big advantage that SSTDR measurements have over other methods is the ability to be connected to energized or live wires (currently up to 1kV) thereby enabling online monitoring of cables. SSTDR has been used successfully in several applications, e.g., aircraft, rail, and photovoltaic systems. In this work FDR and SSTDR cable assessment techniques were used to characterize a variety of cable anomalies and faults including: (1) Presence or absence of a motor; (2) Ground faults and short circuit faults; (3) Moist environments and water ingress faults; (4) Accelerated thermal aging. Both shielded and non-shielded cables were evaluated in this report. Offline measurements were made using FDR and online measurements were made by SSTDR for a range of test scenarios. Based on the results across all cable anomalies evaluated in this study, FDR displayed high sensitivity towards cable condition assessment, while SSTDR showed promise for future application in monitoring NPP cable systems. However, further developments are suggested to improve the resolution and sensitivity of SSTDR towards faults and anomalies in low voltage cables.rt presents a comparative
Series connection of semiconductor submodules (SM) in a modular multilevel converter (MMC) makes the MMC prone to open-circuit (OC) IGBT failures inside SMs. If left undetected, these faults degrade the operation of the MMC and lead to its instability. This article proposes a method to detect, localise, and classify single OC SM faults in an MMC using support vector machines (SVM) trained with data obtained from the capacitor voltage balancing block of the MMC control system. The proposed method relies on data extracted from the sorted capacitor voltage arrays of the upper and lower phase arms. Therefore, it does not require extra measurements and hardware. Additionally, it offers a fixed time for detecting and localising OC SM faults. This method is easy to implement as SVM has a simple decision function. Time-domain simulation case studies are performed on a three-phase nine-level MMC to evaluate the performance of the proposed method.
A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss. The invention provides ultrafast response to a short circuit fault (even faster than solid-state circuit breakers and much faster than hybrid circuit breakers), significantly reduced overcurrent stress in the power system, and/or ultralow conduction power losses.
Here, as quantum computing hardware becomes more complex with ongoing design innovations and growing capabilities, the quantum computing community needs increasingly powerful techniques for fabrication failure root-cause analysis. This is especially true for trapped-ion quantum computing. As trapped-ion quantum computing aims to scale to thousands of ions, the electrode numbers are growing to several hundred, with likely integrated photonic components also adding to the electrical and fabrication complexity, making faults even harder to locate. In this work, we used a high-resolution quantum magnetic imaging technique, based on nitrogen-vacancy centers in diamond, to investigate short-circuit faults in an ion trap chip. We imaged currents from these short-circuit faults to ground and compared them to intentionally created faults, finding that the root cause of the faults was failures in the on-chip trench capacitors. This work, where we exploited the performance advantages of a quantum magnetic sensing technique to troubleshoot a piece of quantum computing hardware, is a unique example of the evolving synergy between emerging quantum technologies to achieve capabilities that were previously inaccessible.
A formally verified implementation of the 'oral messages' algorithm of Pease, Shostak, and Lamport is described. An abstract implementation of the algorithm is verified to achieve interactive consistency in the presence of faults. This abstract characterization is then mapped down to a hardware level implementation which inherits the fault-tolerant characteristics of the abstract version. All steps in the proof were checked with the Boyer-Moore theorem prover. A significant results is the demonstration of a fault-tolerant device that is formally specified and whose implementation is proved correct with respect to this specification. A significant simplifying assumption is that the redundant processors behave synchronously. A mechanically checked proof that the oral messages algorithm is 'optimal' in the sense that no algorithm which achieves agreement via similar message passing can tolerate a larger proportion of faulty processor is also described.