Analog quantizing circuit.
Analog circuit simulating quantization for analog simulation of hybrid control system, showing quantized output and error signal for wave forcing function
Coon, T. R.↗
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An all digital implementation of a modified Hamming net for video compression with prediction and quantization circuits
The hardware and algorithms used to vector quantize (VQ) predicted pixel intensity differences for real-time video compression are described. The hardware is designed for rapid vector quantization performance, which entails the development of application-specific associative memory circuits. A modified DPCM algorithm is originally examined to determine how neural circuitry could enhance its operation. It was determined that quantization and encoding could be improved by consolidating these two functions into one, and by increasing the amount of information (i.e. number of pixels) quantized at a time. The result is a predictive scheme that vector quantizes differential values. Some of the disadvantages of VQ algorithms are solved using associative memories. The video compression algorithm and the associative memory design are described.
Kaul, Richard↗
Resonant Tunneling Analog-To-Digital Converter
As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.
Broekaert, T. P. E.↗
Optical systolic array processor using residue arithmetic
The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.
Jackson, J.↗
Rate-of-change limiter for quantized signals
Analog circuit is employed to smooth change between levels of quantized voltage signal without adversely affecting its fidelity. Circuit is applicable to units requiring interface between digital and analog systems such as automated manufacturing systems or industrial robots.
Streuding, G. C.↗
A CMOS Imager with Focal Plane Compression using Predictive Coding
This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.
Leon-Salas, Walter D.↗
On an extension of Mullin and Jury's method
Actuating signal at sampling instants determined in phase plane by Mullin-Jury method for sampled data feedback containing quantizer and zero order hold circuit
Klepl, M. J.↗
Reduction of quantization error in measurement of frequency
Method reduces quantization errors using new digital circuit. Circuit provides very high resolution (10 to the minus 2nd power to 10 to the minus 3rd power Hz) without high-speed counters. It lends itself to microminaturization and is simple to construct. Unknown frequency is compared to standard frequency by means of zero-crossing coincidence-detecting circuit.
Nossen, E. J.↗
Learning and optimization with cascaded VLSI neural network building-block chips
To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.
Duong, T.↗
Nanowire Photovoltaic Devices
Firefly Technologies, in collaboration with the Rochester Institute of Technology and the University of Wisconsin-Madison, developed synthesis methods for highly strained nanowires. Two synthesis routes resulted in successful nanowire epitaxy: direct nucleation and growth on the substrate and a novel selective-epitaxy route based on nanolithography using diblock copolymers. The indium-arsenide (InAs) nanowires are implemented in situ within the epitaxy environment-a significant innovation relative to conventional semiconductor nanowire generation using ex situ gold nanoparticles. The introduction of these nanoscale features may enable an intermediate band solar cell while simultaneously increasing the effective absorption volume that can otherwise limit short-circuit current generated by thin quantized layers. The use of nanowires for photovoltaics decouples the absorption process from the current extraction process by virtue of the high aspect ratio. While no functional solar cells resulted from this effort, considerable fundamental understanding of the nanowire epitaxy kinetics and nanopatterning process was developed. This approach could, in principle, be an enabling technology for heterointegration of dissimilar materials. The technology also is applicable to virtual substrates. Incorporating nanowires onto a recrystallized germanium/metal foil substrate would potentially solve the problem of grain boundary shunting of generated carriers by restricting the cross-sectional area of the nanowire (tens of nanometers in diameter) to sizes smaller than the recrystallized grains (0.5 to 1 micron(exp 2).
Forbes, David↗
VLSI Processor For Vector Quantization
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
Tawel, Raoul↗
Analog-to-digital converter
An analog to digital converter circuit arrangement is reported that is suitable for use in ultra fast pulse height analysis. The circuit uses series connected tunnel diodes to quantize a voltage signal into discrete levels.
Lewyn, L. L.↗
Real-time demonstration hardware for enhanced DPCM video compression algorithm
The lack of available wideband digital links as well as the complexity of implementation of bandwidth efficient digital video CODECs (encoder/decoder) has worked to keep the cost of digital television transmission too high to compete with analog methods. Terrestrial and satellite video service providers, however, are now recognizing the potential gains that digital video compression offers and are proposing to incorporate compression systems to increase the number of available program channels. NASA is similarly recognizing the benefits of and trend toward digital video compression techniques for transmission of high quality video from space and therefore, has developed a digital television bandwidth compression algorithm to process standard National Television Systems Committee (NTSC) composite color television signals. The algorithm is based on differential pulse code modulation (DPCM), but additionally utilizes a non-adaptive predictor, non-uniform quantizer and multilevel Huffman coder to reduce the data rate substantially below that achievable with straight DPCM. The non-adaptive predictor and multilevel Huffman coder combine to set this technique apart from other DPCM encoding algorithms. All processing is done on a intra-field basis to prevent motion degradation and minimize hardware complexity. Computer simulations have shown the algorithm will produce broadcast quality reconstructed video at an average transmission rate of 1.8 bits/pixel. Hardware implementation of the DPCM circuit, non-adaptive predictor and non-uniform quantizer has been completed, providing realtime demonstration of the image quality at full video rates. Video sampling/reconstruction circuits have also been constructed to accomplish the analog video processing necessary for the real-time demonstration. Performance results for the completed hardware compare favorably with simulation results. Hardware implementation of the multilevel Huffman encoder/decoder is currently under development along with implementation of a buffer control algorithm to accommodate the variable data rate output of the multilevel Huffman encoder. A video CODEC of this type could be used to compress NTSC color television signals where high quality reconstruction is desirable (e.g., Space Station video transmission, transmission direct-to-the-home via direct broadcast satellite systems or cable television distribution to system headends and direct-to-the-home).
Bizon, Thomas P.↗
Video data compression using artificial neural network differential vector quantization
An artificial neural network vector quantizer is developed for use in data compression applications such as Digital Video. Differential Vector Quantization is used to preserve edge features, and a new adaptive algorithm, known as Frequency-Sensitive Competitive Learning, is used to develop the vector quantizer codebook. To develop real time performance, a custom Very Large Scale Integration Application Specific Integrated Circuit (VLSI ASIC) is being developed to realize the associative memory functions needed in the vector quantization algorithm. By using vector quantization, the need for Huffman coding can be eliminated, resulting in superior performance against channel bit errors than methods that use variable length codes.
Krishnamurthy, Ashok K.↗
An Analog Processor for Image Compression
This paper describes a novel analog Vector Array Processor (VAP) that was designed for use in real-time and ultra-low power image compression applications. This custom CMOS processor is based architectually on the Vector Quantization (VQ) algorithm in image coding, and the hardware implementation fully exploits the inherent parallelism built-in the VQ algorithm.
Vector Array Processor VAP analog processor image ↗
Description of the three axis low-g accelerometer package
The three axis low-g accelerometer package designed for use on the Space Processing Application Rocket (SPAR) Program is described. The package consists of the following major sections: (1) three Kearfott model 2412 accelerometers mounted in an orthogonal triad configuration on a temperature controlled, thermally isolated cube, (2) the accelerometer servoelectronics (printed circuit cards PC-6 through PC-12), and (3) the signal conditioner (printed circuit cards PC-15 and PC-16). The measurement range is 0 + or - 0.031 g with a quantization of 1.1 x 10 to the 7th power g. The package was flown successfully on six SPAR launches with the Black Brant booster. These flights provide approximately 300 s of free fall or zero-g environment.
Amalavage, A. J.↗
An 8-PSK TDMA uplink modulation and coding system
The combination of 8-phase shift keying (8PSK) modulation and greater than 2 bits/sec/Hz drove the design of the Nyquist filter to one specified to have a rolloff factor of 0.2. This filter when built and tested was found to produce too much intersymbol interference and was abandoned for a design with a rolloff factor of 0.4. The preamble is limited to 100 bit periods of the uncoded bit period of 5 ns for a maximum preamble length of 500 ns or 40 8PSK symbol times at 12.5 ns per symbol. For 8PSK modulation, the required maximum degradation of 1 dB in -20 dB cochannel interference (CCI) drove the requirement for forward error correction coding. In this contract, the funding was not sufficient to develop the proposed codec so the codec was limited to a paper design during the preliminary design phase. The mechanization of the demodulator is digital, starting from the output of the analog to digital converters which quantize the outputs of the quadrature phase detectors. This approach is amenable to an application specific integrated circuit (ASIC) replacement in the next phase of development.
Ames, S. A.↗
Image processing using Gallium Arsenide (GaAs) technology
The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.
Miller, Warner H.↗