SEARCH · Search NASA

Results for “circuit topology design”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records

All sources NASA NTRS DOE OSTI

DOE OSTI2026

Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning

Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.

Lu, Haoshu [New Jersey Institute of Technology (NJ↗

NASA NTRS1996

Design and Analysis of Broad-Band Fixed-Tuned Submillimeter-Waveguide Multipliers using MMIC Style Circuit Topology

The design and analysis of varactor diode doubler, quadrupler and cascaded doubler circuits for 320 and 640 GHz have been completed. A new approach has been employed to produce a tunerless waveguide mount with a very flexible, frequency scaleable, MMIC style multiplier circuit. The concept, design, predicted performance and measurements on some of the constituent mount elements are presented.

varactor diode doubler MMIC style multiplier circu↗

DOE OSTI2022

Topological current divider in a Chern insulator junction

A Chern insulator is a two-dimensional material that hosts chiral edge states produced by the combination of topology with time reversal symmetry breaking. Such edge states are perfect one-dimensional conductors, which may exist not only on sample edges, but on any boundary between two materials with distinct topological invariants (or Chern numbers). Engineering of such interfaces is highly desirable due to emerging opportunities of using topological edge states for energy-efficient information transmission. Here, we report a chiral edge-current divider based on Chern insulator junctions formed within the layered topological magnet MnBi 2 Te 4 . We find that in a device containing a boundary between regions of different thickness, topological domains with different Chern numbers can coexist. At the domain boundary, a Chern insulator junction forms, where we identify a chiral edge mode along the junction interface. We use this to construct topological circuits in which the chiral edge current can be split, rerouted, or switched off by controlling the Chern numbers of the individual domains. Our results demonstrate MnBi 2 Te 4 as an emerging platform for topological circuits design.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2022

Power Converter Circuit Design Automation using Parallel Monte Carlo Tree Search

The tidal waves of modern electronic/electrical devices have led to increasing demands for ubiquitous application-specific power converters. A conventional manual design procedure of such power converters is computation- and labor-intensive, which involves selecting and connecting component devices, tuning component-wise parameters and control schemes, and iteratively evaluating and optimizing the design. To automate and speed up this design process, we propose an automatic framework that designs custom power converters from design specifications using Monte Carlo Tree Search. Specifically, the framework embraces the upper-confidence-bound-tree (UCT), a variant of Monte Carlo Tree Search, to automate topology space exploration with circuit design specification-encoded reward signals. Moreover, our UCT-based approach can exploit small offline data via the specially designed default policy and can run in parallel to accelerate topology space exploration. Further, it utilizes a hybrid circuit evaluation strategy to substantially reduce design evaluation costs. Empirically, we demonstrated that our framework could generate energy-efficient circuit topologies for various target voltage conversion ratios. Compared to existing automatic topology optimization strategies, the proposed method is much more computationally efficient --- the sequential version can generate topologies with the same quality while being up to 67% faster. Here, the parallelization schemes can further achieve high speedups compared to the sequential version.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS2004

Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration

Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.

digital circuits designs↗

NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗

DOE OSTI2023

AutoTG: Reinforcement Learning-Based Symbolic Optimization for AI-Assisted Power Converter Design

Power converters are pervasive in modern electronic component design. They can be found in all electronic devices from household appliances and cellphone chargers to vehicles. Currently, designing new circuit topologies is hard because it requires human expertise based on experience and is difficult to automate. However, artificial-intelligence-assisted design can significantly facilitate the development of new power converters and/or improve the final result. Intelligently designed highly efficient power converters can have a significant effect on many important attributes, such as power efficiency, layout size, cost, heat dissemination, energy requirements, etc. We propose Autonomous Topology Generator (AutoTG), a reinforcement-learning-based framework that generates power converter topology candidates based on user specifications, optimized for user preferences. By modeling power converter design as a symbolic optimization problem, we sequentially sample components in an autoregressive manner until new topologies are formed, providing both the topology specification and the sizing (magnitude of each component parameter) of the proposed power converter. Here, we provide an empirical evaluation and show that AutoTG is able to generate varied high-efficiency topologies within component restrictions based on user input and show that previously unknown topologies can be found for further evaluation.

(AI)-based design↗

NASA NTRS2005

Evolvable hardware system at extreme low temperatures

This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hardening-by-process and hardening-by-design, 'hardening-by-reconfiguration ', when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive selfreconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. This paper demonstrates this technique for circuit evolution and recovery at liquid nitrogen temperatures (-196.6 (deg)C). In addition, preliminary tests are performed to assess the survivability limitations of the evolutionary processor at extreme low temperatures.

evolvable harware↗

NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗

NASA NTRS2015

Low-Cost, High-Performance Hall Thruster Support System

Colorado Power Electronics (CPE) has built an innovative modular PPU for Hall thrusters, including discharge, magnet, heater and keeper supplies, and an interface module. This high-performance PPU offers resonant circuit topologies, magnetics design, modularity, and a stable and sustained operation during severe Hall effect thruster current oscillations. Laboratory testing has demonstrated discharge module efficiency of 96 percent, which is considerably higher than current state of the art.

Hesterman, Bryce↗

DOE OSTI2024

LENS: Learning Enabled Network Synthesis

RTRC and UMD have developed novel machine learning based methods under the ARPA-E DIFFERENTIATE program for rapid acceleration of hypothesis generation in complex architecture design spaces involving both discrete choices of component inclusion and interconnection and continuous parametric decisions. The project named Learning Enabled Network Synthesis (LENS) further demonstrated the developed methods on challenging electrical power converter design problems by identifying the most suitable circuit topologies and simultaneously selecting the most appropriate components to achieve optimized design of power converter with improved performances. We demonstrated that LENS could enable exploration of very large design space of circuit topologies and components by addressing the limitations of conventional design process in non-linear, high switching speed, multi-dimensional power converter design and optimization. The key innovation developed in LENS is the seamless integration of statistical learning and logical reasoning techniques and building on the individual strengths of these techniques for rapid hypothesis discovery. The main component of LENS comprises of: 1) Graph Reasoning Engine (GRE) to enforce composition rules that rapidly reject all discrete architectures that are composed incorrectly and generates an adaptive database of feasible designs which can be used by ML modules, 2) Graph Generative Learning module which is a deep neural network based generative model for graph architectures which can enable design space exploration beyond the dataset generated by the GRE, 3) Graph Reduced Order Model (ROM) for graph domains for accelerating computation of output metrics, and 4) Active learning and Rule Discovery module for sample efficient learning and extracting logical rules from the learned ML models which will be integrated in the GRE to enhance the filtering effectiveness. LENS approach can be applied to any design domains where designs can be represented as multi-attribute graphs. The LENS team integrated the various technical innovations listed above into an optimization pipeline and exercised the optimization pipeline on the converter design problem. The LENS project demonstrated that the developed AI/ML technologies can be used to generate novel converter circuits >45x faster than experts on chosen use-cases. This can enable faster design space exploration and identification of new designs which are not considered by experts due to the increasing design space complexity. This has significant potential impact on the public and energy needs of the country. It is currently estimated that 30% of all electrical powers generated passes through power converters. The future estimate is that 80% of all power generated would be passing through converters. LENS fills a critical gap in this space since by accelerating the design process the designers would be able to generate more efficient converters which can lead to significant energy savings for the country.

42 ENGINEERING↗

NASA NTRS2010

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

Burns, Bradley M.↗

NASA NTRS2010

A 311-GHz Fundamental Oscillator Using InP HBT Technology

This oscillator uses a single-emitter 0.3- m InP heterojunction bipolar transistor (HBT) device with maximum frequency of oscillation (fmax) greater than 500 GHz. Due to high conductor and substrate losses at submillimeterwave frequencies, a primary challenge is to efficiently use the intrinsic device gain. This was done by using a suitable transmission-line media and circuit topology. The passive components of the oscillator are realized in a twometal process with benzocyclobutene (BCB) used as the primary transmission line dielectric. The circuit was designed using microstrip transmission lines. The oscillator is implemented in a common-base topology due to its inherent instability, and the design includes an on-chip resonator, outputmatching circuitry, and an injection-locking port, the port being used to demonstrate the injection-locking prin ciple. A free-running frequency of 311.6 GHz has been measured by down-converting the signal. Ad di tionally, injection locking has been successfully demonstrated with up to 17.8 dB of injection-locking gain. The injection-locking reference signal is generated using a 2 20 GHz frequency synthesizer, followed by a doubler, active tripler, a W-band amplifier, and then a passive tripler. Therefore, the source frequency is multiplied 18 times to obtain a signal above 300 GHz that can be used to injection lock the oscillator. Measurement shows that injection locking has improved the phase noise of the oscillator and can be also used for synchronizing a series of oscillators. A signal conductor is implemented near the BCP -InP interface and the topside of the BCB layer is fully metallized as a signal ground. Because the fields are primarily constrained in the lower permittivity BCB region, this type of transmission line is referred to as an inverted microstrip. In addition, both common-emitter and commonbase circuits were investigated to determine optimum topology for oscillator design. The common -base topology required smaller amount of feedback than the common-emitter design, therefore preserving device gain, and was chosen for the oscillator design. The submillimeter-wave region offers several advantages for sensors and communication systems, such as high resolution and all-weather imaging due to the short-wavelength, and improved communication speeds by access to greater frequency bandwidth. This oscillator circuit is a prototype of the first HBT oscillator operating above 300 GHz. Additional development is necessary to increase the output power of the circuit for radar and imaging applications.

Gaier, Todd↗

NASA NTRS1984

A Battery Charger and State of Charge Indicator

A battery charger which has a full wave rectifier in series with a transformer isolated 20 kHz dc-dc converter with high frequency switches, which are programmed to actively shape the input dc line current to be a mirror image of the ac line voltage is discussed. The power circuit operates at 2 kW peak and 1 kW average power. The BC/SCI has two major subsystems: (1) the battery charger power electronics with its controls; and (2) a microcomputer subsystem which is used to acquire battery terminal data and exercise the state of charge software programs. The state of charge definition employed is the energy remaining in the battery when extracted at a 10 kW rate divided by the energy capacity of a fully charged new battery. The battery charger circuit is an isolated boost converter operating at an internal frequency of 20 kHz. The switches selected for the battery charger are the single most important item in determining its efficiency. The combination of voltage and current requirements dictate the use of high power NPN Darlington switching transistors. The power circuit topology is a three switch design which utilizes a power FET on the center tap of the isolation transformer and the power Darlingtons on each of the two ends. An analog control system is employed to accomplish active input current waveshaping as well as the necessary regulation.

Latos, T. S.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System (HT-SSEP) to Enable Lower Cost NASA Science Missions

Discusses progress at the NASA Glenn Research Center (GRC) in the development and demonstration of an integrated high-propellant throughput small spacecraft electric propulsion (HT-SSEP) system based on a Hall-effect thruster. A center-mounted cathode and an innovative magnetic circuit topology were implemented in the design of the Hall-effect thruster to achieve high-propellant throughput, high performance, and efficient packaging. To minimize technical risk, the HT-SSEP development approach sought to limit design features and materials to those with a clear path-to-flight. A propellant throughput capability of greater than 100 kilograms at a minimum thruster efficiency of 50 percent was targeted. The proof-of-concept NASA-H64M laboratory model (LM) thruster was designed, fabricated, and tested at GRC in fiscal year 2018. The thruster development leveraged heritage Hall-effect thruster design and manufacturing processes wherever appropriate. Recent NASA advances in Hall-effect thruster technology were also leveraged. A scalable discharge power supply (DPS) capable of powering the H64M-LM was developed, then demonstrated as part of an integrated system test. The DPS uses commercial off-the-shelf components with spaceflight equivalents. A keeper supply with DC ignitor was breadboarded, then demonstrated with a laboratory cathode. Finally, feed system trade studies were performed to ascertain what feed system architecture might be appropriate for an HT-SSEP system. This paper details the motivations for the project, the development approach, the chosen sub-system architectures, design considerations, and test results.

Benavides, Gabriel↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

This paper describes recent progress at the NASA Glenn Research Center (GRC) in the development and demonstration of an integrated high-propellant throughput small spacecraft electric propulsion (HT-SSEP) system based on a Hall-effect thruster. A center-mounted cathode and an innovative magnetic circuit topology were implemented in the design of the Hall-effect thruster to achieve high-propellant throughput, high performance, and efficient packaging. To minimize technical risk, the HT-SSEP development approach sought to limit design features and materials to those with a clear path-to-flight. A propellant throughput capability of greater than 100 kg at a minimum thruster efficiency of 50% was targeted. The proof-of-concept NASA-H64M laboratory model (LM) thruster was designed, fabricated, and tested at GRC in fiscal year 2018. The thruster development leveraged heritage Hall-effect thruster design and manufacturing processes wherever appropriate. Recent NASA advances in Hall-effect thruster technology were also leveraged. A scalable discharge power supply (DPS) capable of powering the H64M-LM was developed, then demonstrated as part of an integrated system test. The DPS uses commercial off-the-shelf components with spaceflight equivalents. A keeper supply with DC ignitor was breadboarded, then demonstrated with a laboratory cathode. Finally, feed system trade studies were performed to ascertain what feed system architecture might be appropriate for an HT-SSEP system. This paper details the motivations for the project, the development approach, the chosen sub-system architectures, design considerations, and test results.

Benavides, Gabriel F.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

Benavides, Gabriel F.↗

NASA NTRS1994

Silicon device performance measurements to support temperature range enhancement

Silicon based power devices can be used at 200 C. The device measurements made during this program show a predictable shift in device parameters with increasing temperature. No catastrophic or abrupt changes occurred in the parameters over the temperature range. As expected, the most dramatic change was the increase in leakage currents with increasing temperature. At 200 C the leakage current was in the milliAmp range but was still several orders of magnitude lower than the on-state current capabilities of the devices under test. This increase must be considered in the design of circuits using power transistors at elevated temperature. Three circuit topologies have been prototyped using MOSFET's and IGBT's. The circuits were designed using zero current or zero voltage switching techniques to eliminate or minimize hard switching of the power transistors. These circuits have functioned properly over the temperature range. One thousand hour life data have been collected for two power supplies with no failures and no significant change in operating efficiency. While additional reliability testing should be conducted, the feasibility of designing soft switched circuits for operation at 200 C has been successfully demonstrated.

Bromstead, James↗