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Results for “common-mode voltage injection”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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3 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Capacitor Voltage Ripple Estimation and Optimal Sizing of Modular Multi-Level Converters for Variable-Speed Drives

This article deals with the sizing of submodule capacitors for modular multilevel converters (MMCs) used for variable speed drives for medium voltage and high voltage electric machines. Variable speed drives are required to run over a wide frequency range from zero to a few hundred Hz or even over 1 kHz. Under low frequency operation (<30 Hz), a large current ripple flowing through the MMC submodule capacitors will cause significant capacitor voltage fluctuation. This article proposes an optimal submodule capacitor selection method based on the common-mode voltage injection. The proposed sizing model includes two functions: 1) accurately estimating the capacitor voltage ripple based on the drive system parameters; and 2) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and experimental results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

42 ENGINEERING↗
DOE OSTI2022

Immunity Study: Port Impedance Measurement of PMU and PCI testing under EMP

Phasor Measurement Units (PMUs) are critical for the Wide Area Measurement System (WAMS), especially for real-time grid monitoring, disturbance location, and situation awareness. Once they are damaged, the stable operation of the power system will be affected directly and greatly. Therefore, it is urgent and necessary to study their immunity to electromagnetic pulse (EMP) events. In this paper, an effective impedance measurement scheme is proposed for port impedance measurement of PMU. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Then circuit of pulsed current generator is established to generate damping sinusoid and double exponential wave applied to the port. Finally, by using measured impedance as a load of the generator, the voltage and current responses of different ports are calculated in the pulsed current injection (PCI) testing simulation. Results show that common-mode impedance is large and differential mode impedance is small. The critical condition will appear in the common mode for voltage and differential mode for current.

Zhang, Liang↗
DOE OSTI2019

Reduced Common-Mode Voltage PWM Scheme for Full-SiC Three-Level Uninterruptible Power Supply With Small DC-Link Capacitors

In this article, a pulsewidth modulation (PWM) scheme for three-level full-SiC uninterruptible power supplies is developed to achieve a high power density. Two key passive components are selected for size reduction of the ac-ac stage: common-mode (CM) EMI filter, and dc-link capacitors. To reduce the CM noise, a new vector combination is proposed based on synchronous switching among three-phases. The proposed combinations align CM voltage (CMV) to be a single pulse per switching period. Owing to the simple shape, CMV cancellation between a three-level rectifier and inverter can be maximally utilized. A transition between the three combinations can control the drift of neutral point voltage. An equivalent carrier-based implementation is developed. Second, a simple algorithm to compensate neutral point voltage fluctuation is proposed both for differential mode (DM) and CM output voltage. Low-order harmonics on three-phase currents and an additional high-frequency CM noise by misaligned switching instant can be eliminated. The proposed compensation can be implemented by a simple correction on carrier slopes and injected zero-sequence voltage. The proposed PWM scheme is verified with 20-kW full-SiC UPS switching at 60 kHz with 140 μF dc-link capacitors.

42 ENGINEERING↗