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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming

Advances in novel hardware devices and architectures allow Spiking Neural Network (SNN) evaluation using ultra-low power, mixed-signal, memristor crossbar arrays. As individual network sizes quickly scale beyond the dimensional capabilities of single crossbars, networks must be mapped onto multiple crossbars. Crossbar sizes within modern Memristor Crossbar Architectures (MCAs) are determined predominately not by device technology but by network topology; more, smaller crossbars consume less area thanks to the high structural sparsity found in larger, brain-inspired SNNs. Motivated by continuing increases in SNN sparsity due to improvements in training methods, we propose utilizing heterogeneous crossbar sizes to further reduce area consumption. This approach was previously unachievable as prior compiler studies only explored solutions targeting homogeneous MCAs. Our work improves on the state-of-the-art by providing Integer Linear Programming (ILP) formulations supporting arbitrarily heterogeneous architectures. By modeling axonal interactions between neurons, our methods produce better mappings while removing inhibitive a priori knowledge requirements. We first show a 16.7-27.6% reduction in area consumption for square-crossbar homogeneous architectures. Then, we demonstrate 66.9-72.7% further reduction when using a reasonable configuration of heterogeneous crossbar dimensions. Next, we present a new optimization formulation capable of minimizing the number of inter-crossbar routes. When applied to solutions already near-optimal in area, an 11.9-26.4% routing reduction is observed without impacting area consumption. Finally, we present a profile-guided optimization capable of minimizing the number of runtime spikes between crossbars. Compared to the best-area-then-route optimized solutions, we observe a further 0.5-14.8% inter-crossbar spike reduction while requiring 1–3 orders of magnitude less solver time.

Pohl, Devin [ORNL] (ORCID:0009000040149027)↗

PowerMappeR: Power-Optimized Mapping of SNNs onto ReRAM Crossbars coupled via Packet-Switched NoCs

Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved SNN training methods increase accuracy and structural sparsity in networks despite growing problem sizes. Finally, compilers leverage these attributes to minimize area and inter-crossbar communication while mapping large SNNs to sophisticated architectures. However, for compiler-driven co-design to realize increasingly complex and profitable optimizations, a compile-time view of power consumption is critical. We present PowerMappeR to express and optimize over mapping-, architecture-, and device-specific power consumption information. By modeling the dynamic power of well-established components, we develop an integer linear programming (ILP)-based, encoding-agnostic, parametric power estimation model. Using this model, we demonstrate practical improvements in area and inter-crossbar communication by 0%–9.5% and 1.4%–5.1%, respectively. We also limit hotspot formation during optimization, achieving comparable or better results in targeted metrics with up to 96.4%–97.1% restriction of hotspot magnitude. Finally, we introduce profile-guided formulations to reduce worst-case and expected-case hotspot magnitude by 40.7%–69.5% and 40.6%–56.3%, respectively. Optimizing worst-case hotspot magnitude incidentally improves expected-case magnitude by 10.85%–33.45%. Reciprocally, optimizing expected-case magnitude incidentally improves worst-case magnitude by 4.33%–39.87%. Validation against hardware simulators confirms that PowerMappeR can decrease dynamic power consumption by 12.6%–27.3%.

Pohl, Devin [ORNL] (ORCID:0009000040149027)↗

Neural network architecture for crossbar switch control

A Hopfield neural network architecture for the real-time control of a crossbar switch for switching packets at maximum throughput is proposed. The network performance and processing time are derived from a numerical simulation of the transitions of the neural network. A method is proposed to optimize electronic component parameters and synaptic connections, and it is fully illustrated by the computer simulation of a VLSI implementation of 4 x 4 neural net controller. The extension to larger size crossbars is demonstrated through the simulation of an 8 x 8 crossbar switch controller, where the performance of the neural computation is discussed in relation to electronic noise and inhomogeneities of network components.

Troudet, Terry P.↗

Time-multiplexed, optically-addressed, gigabit optical crossbar switch

A time-multiplexed, optically-addressed, crossbar switch (38) is provided using a two-dimensional, optically-addressed, reflective spatial light modulator (O-SLM) (20). Since the optical addressing is time-multiplexed, only N addressing lines are required for an N.times.N crossbar, rather than the N.sup.2 lines needed in the prior art. This reduction in addressing lines makes possible the development of enormous crossbar switches, such as 100.times.100, for the first time. In addition, since data paths remain entirely in the optics domain, data speeds can reach the multi-gigabit level. In the switch, a row (40) of N inputs (42) at the read wavelength is spread over one axis of the O-SLM. The light is refocused along the other axis to an output array (48) of detectors (50), so that each input has the potential to talk to any one output. The O-SLM is normally off, i.e., non-reflective, so that the output is, in the absence of an input signal, zero. A one-dimensional array (52) of lasers (54) at the write wavelength is imaged onto the O-SLM. Each laser scans across an entire row of the O-SLM; where the laser is on, it turns on a portion of the O-SLM and establishes a connection between a particular input and a particular output. A full row is scanned in a time much shorter than the response time of the O-SLM, so that state of the O-SLM is capacitively stored and dynamically refreshed. The scanning is accomplished by tuning the wavelength of the laser and passing it through a grating, which sweeps the beam in space.

Lang, Robert J.↗

Integration of Ag-CBRAM crossbars and Mott ReLU neurons for efficient implementation of deep neural networks in hardware

In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.

Mott insulators↗

Design Space Exploration of Ferroelectric Tunnel Junction Toward Crossbar Memories

We perform a simulation-based analysis on the potential of emerging ferroelectric tunnel junctions (FTJs) as a memory device for crossbar arrays. Though FTJs are promising due to their low power switching characteristics compared to other emerging technologies, the greatest challenge for FTJs is the tradeoff between integration density and read performance. Our analysis highlights the need to co-optimize the ferroelectric thickness of the FTJ and read/write voltages to achieve proper functionality at large array sizes. Our analysis shows that FTJ-based crossbar achieves 93% higher sense margin at isoread power of 116 nW (per bit), but this FTJ design comes at a cost of 9.28× higher write power at isowrite time of 250 ns. In response, we study the potential tradeoffs of design points outside the feasible region to understand what device characteristics are desired to overcome such challenges.

Jao, Nicholas↗

Vector-Matrix Multiplication Engine for Neuromorphic Computation with a CBRAM Crossbar Array [Slides]

The core function of many neural network algorithms is the dot product, or vector matrix multiply (VMM) operation. Crossbar arrays utilizing resistive memory elements can reduce computational energy in neural algorithms by up to five orders of magnitude compared to conventional CPUs. Moving data between a processor, SRAM, and DRAM dominates energy consumption. By utilizing analog operations to reduce data movement, resistive memory crossbars can enable processing of large amounts of data at lower energy than conventional memory architectures.

97 MATHEMATICS AND COMPUTING↗

Control means for a solid state crossbar switch

A control system for a solid state crossbar switch which allows a plurality of switch control and interrogation functions to be implemented by time sharing related circuitry is described. The crossbar switch includes a plurality of X ports and Y ports, each X-Y port intersection designating a specific X-Y intersection latch which controls a plurality of associated switches for interconnecting one set of data lines associated with the X port to another set of data lines associated with the Y port. The control system continuously and sequentially addresses each of the X-Y intersection latches at a 10 megahertz rate. During this addressing, the control circuitry includes a capability for interrogating each intersection latch for determining which are in a set condition, ensuring that only one X-Y intersection latch is set on an X row and Y column defining that latch, resetting all of the X-Y intersection latches, and determining which of the X-Y intersection latches are in a set condition.

Anderson, T. O.↗

Proton Single Event Effects (SEE) Testing of the Myrinet Crossbar Switch and Network Interface Card

As part of the Remote Exploration and Experimentation Project (REE), work was performed to do a proton SEE (Single Event Effect) evaluation of the Myricom network protocol system (Myrinet). This testing included the evaluation of the Myrinet crossbar switch and the Network Interface Card (NIC). To this end, two crossbar switch devices and five components in the NIC were exposed to the proton beam at the University of California at Davis Crocker Nuclear Laboratory (CNL).

Howard, James W., Jr.↗

Bioelectrochemical crossbar architecture screening platform for extracellular electron transfer

Electroactive microbes can serve as living components in bioelectronic devices, where their unique ability to transfer electrons enables applications in sensing, energy conversion, and synthesis, but they remain challenging to engineer because the bioelectrochemical systems (BESs) used for characterization are low throughput. Here, we present a bioelectrochemical crossbar architecture screening platform (BiCASP) that uses stacked and orthogonally arrayed electrodes to enable individual sample selection for characterization in arrayed formats. This device reports on the current generated by electroactive bacteria on the minute timescale, decreasing the time for data acquisition by several orders of magnitude compared to conventional BESs. This device increases the throughput of screening engineered biological components in cells, identifying mutants of the membrane protein wire MtrA in Shewanella oneidensis that retain the ability to support extracellular electron transfer (EET). BiCASP may be integrated with bioelectronics that need directed evolution of electroactive proteins.

Shewanella↗

A solid state crossbar switch for automatic analog computer patching

An all-electronic crossbar switch consisting of FET series-shunt switches inside the feedback loops of operational amplifiers was designed and constructed. Time-shared solution of five different differential equations was obtained by using four integrators on ASTRAC 2, with a new solution being generated 250 times per second.

Yagi, A.↗

Solid-State Crossbar Switch

Combines analog and digital circuits for multiline/multiport switching. Bidirectional solid-state crossbar switch provides interfacing and switching for 16 X24 coordinate ports for 16 parallel signal lines. Intended for rapid manual-controlled or computer controlled reconfiguration of distributed computing systems.

Anderson, T. O.↗

Crossbar Switches For Optical Data-Communication Networks

Optoelectronic and electro-optical crossbar switches called "permutation engines" (PE's) developed to route packets of data through fiber-optic communication networks. Basic network concept described in "High-Speed Optical Wide-Area Data-Communication Network" (NPO-18983). Nonblocking operation achieved by decentralized switching and control scheme. Each packet routed up or down in each column of this 5-input/5-output permutation engine. Routing algorithm ensures each packet arrives at its designated output port without blocking any other packet that does not contend for same output port.

Monacos, Steve P.↗

Non-blocking crossbar permutation engine with constant routing latency

The invention is embodied in an N x N crossbar for routing packets from a set of N input ports to a set of N output ports, each packet having a header identifying one of the output ports as its destination, including a plurality of individual links which carry individual packets. Each link has a link input end and a link output end, a plurality of switches. Each of the switches has at least top and bottom switch inputs connected to a corresponding pair of the link output ends and top and bottom switch outputs connected to a corresponding pair of link input ends, whereby each switch is connected to four different links. Each of the switches has an exchange state which routes packets from the top and bottom switch inputs to the bottom and top switch outputs, respectively, and a bypass state which routes packets from the top and bottom switch inputs to the top and bottom switch outputs, respectively. A plurality of individual controller devices governing respective switches for sensing from a header of a packet at each switch input for the identity of the destination output port of the packet and selecting one of the exchange and bypass states in accordance with the identity of the destination output port and with the location of the corresponding switch relative to the destination output port.

Monacos, Steve P.↗

Encoding data within a crossbar memory array

In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

Muralimanohar, Naveen↗

Harnessing ML Privacy by Design Through Crossbar Array Non-idealities

Deep Neural Networks (DNNs), handling computeand data-intensive tasks, often utilize accelerators like Resistiveswitching Random-access Memory (RRAM) crossbar for energyefficient in-memory computation. Despite RRAM’s inherent nonidealities causing deviations in DNN output, this study transforms the weakness into strength. By leveraging RRAM non-idealities, the research enhances privacy protection against Membership Inference Attacks (MIAs), which reveal private information from training data. RRAM non-idealities disrupt MIA features, increasing model robustness and revealing a privacy-accuracy tradeoff. Empirical results with four MIAs and DNNs trained on different datasets demonstrate significant privacy leakage reduction with a minor accuracy drop (e.g., up to 2.8% for ResNet-18 with CIFAR-100).

artificial intelligence↗

Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

In this paper, we present a scalable digital hardware accelerator based on non-volatile memory arrays capable of realizing deep convolutional spiking neural networks (SNNs). Our design studies are conducted using a compact model for spin-transfer torque random access memory (STT-RAM) devices. Large networks are realized by tiling multiple cores which communicate by transmitting spike packets via an on-chip routing network. Compared to an equivalent SRAM based core design, we show that the STT-RAM based design achieves nearly 15X higher GSOPS (Synaptic Operations per Second) per Watt per mm 2 making it a promising platform for realizing systems with significant area and power limitations.

Kulkarni, Shruti↗