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At least 19 records

RFID and Memory Devices Fabricated Integrally on Substrates

Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for the deposition of the device. By use of a vacuum arc vapor deposition apparatus, a thin electrically insulating film would first be deposited on the substrate. Subsequent layers of materials would then be deposited and patterned by use of known integrated-circuit fabrication techniques. The total thickness of the deposited layers could be much less than the 100- m thickness of the thinnest state-of-the-art self-contained microchips. Such a thin deposit could be readily concealed by simply painting over it. Both large vacuum chambers for production runs and portable hand-held devices for in situ applications are available.

Schramm, Harry F.↗

Optical processing for semiconductor device fabrication

A new technique for semiconductor device processing is described that uses optical energy to produce local heating/melting in the vicinity of a preselected interface of the device. This process, called optical processing, invokes assistance of photons to enhance interface reactions such as diffusion and melting, as compared to the use of thermal heating alone. Optical processing is performed in a 'cold wall' furnace, and requires considerably lower energies than furnace or rapid thermal annealing. This technique can produce some device structures with unique properties that cannot be produced by conventional thermal processing. Some applications of optical processing involving semiconductor-metal interfaces are described.

Sopori, Bhushan L.↗

Methods for Making an Electroactive Device Fabricated with a Nanotube Film Electrode

Disclosed is a single wall carbon nanotube (SWCNT) film electrode (FE), all-organic electroactive device systems fabricated with the SWNT-FE, and methods for making same. The SWCNT can be replaced by other types of nanotubes. The SWCNT film can be obtained by filtering SWCNT solution onto the surface of an anodized alumina membrane. A freestanding flexible SWCNT film can be collected by breaking up this brittle membrane. The conductivity of this SWCNT film can advantageously be higher than 280 S/cm. An electroactive polymer (EAP) actuator layered with the SWNT-FE shows a higher electric field-induced strain than an EAP layered with metal electrodes because the flexible SWNT-FE relieves the restraint of the displacement of the polymeric active layer as compared to the metal electrode. In addition, if thin enough, the SWNT-FE is transparent in the visible light range, thus making it suitable for use in actuators used in optical devices.

Kang, Jin Ho↗

Nanotube Film Electrode and an Electroactive Device Fabricated with the Nanotube Film Electrode and Methods for Making Same

Disclosed is a single wall carbon nanotube (SWCNT) film electrode (FE), all-organic electroactive device systems fabricated with the SWNT-FE, and methods for making same. The SWCNT can be replaced by other types of nanotubes. The SWCNT film can be obtained by filtering SWCNT solution onto the surface of an anodized alumina membrane. A freestanding flexible SWCNT film can be collected by breaking up this brittle membrane. The conductivity of this SWCNT film can advantageously be higher than 280 S/cm. An electroactive polymer (EAP) actuator layered with the SWNT-FE shows a higher electric field-induced strain than an EAP layered with metal electrodes because the flexible SWNT-FE relieves the restraint of the displacement of the polymeric active layer as compared to the metal electrode. In addition, if thin enough, the SWNT-FE is transparent in the visible light range, thus making it suitable for use in actuators used in optical devices.

Kang, Jin Ho↗

Demonstration of Y1Ba2Cu3O(7-delta) and complementary metal-oxide-semiconductor device fabrication on the same sapphire substrate

We report the first fabrication of active semiconductor and high-temperature superconducting devices on the same substrate. Test structures of complementary MOS transistors were fabricated on the same sapphire substrate as test structures of Y1Ba2Cu3O(7-delta) flux-flow transistors, and separately, Y1Ba2Cu3O(7-delta) superconducting quantum interference devices utilizing both biepitaxial and step-edge Josephson junctions. Both semiconductor and superconductor devices were operated at 77 K. The cofabrication of devices using these disparate yet complementary electronic technologies on the same substrate opens the door for the fabrication of true semiconductive/superconductive hybrid integrated circuits capable of exploiting the best features of each of these technologies.

Burns, M. J.↗

Thin-Film Photovoltaic Device Fabrication

This project will primarily involve the fabrication and characterization of thin films and devices for photovoltaic applications. The materials involved include Il-VI materials such as zinc oxide, cadmium sulfide, and doped analogs. The equipment ot be used will be sputtering and physical evaporations. The types of characterization includes electrical, XRD, SEM and CV and related measurements to establish the efficiency of the devices. The faculty fellow will be involved in a research team composed of NASA and University researchers as well as students and other junior researchers.

Scofield, John H.↗

Silicon carbide semiconductor device fabrication and characterization

A number of basic building blocks i.e., rectifying and ohmic contacts, implanted junctions, MOS capacitors, pnpn diodes and devices, such as, MESFETs on both alpha and beta SiC films were fabricated and characterized. Gold forms a rectifying contact on beta SiC. Since Au contacts degrade at high temperatures, these are not considered to be suitable for high temperature device applications. However, it was possible to utilize Au contact diodes for electrically characterizing SiC films. Preliminary work indicates that sputtered Pt or Pt/Si contacts on beta SiC films are someways superior to Au contacts. Sputtered Pt layers on alpha SiC films form excellent rectifying contacts, whereas Ni layers following anneal at approximately 1050 C provide an ohmic contact. It has demonstrated that ion implantation of Al in substrates held at 550 C can be successfully employed for the fabrication of rectifying junction diodes. Feasibility of fabricating pnpn diodes and platinum gated MESFETs on alpha SiC films was also demonstrated.

Davis, R. F.↗

ITO/InP solar cells: A comparison of devices fabricated by ion beam and RF sputtering of the ITO

This work was performed with the view of elucidating the behavior of indium tin oxide/indium phosphide (ITO/InP) solar cells prepared by RF and ion beam sputtering. It was found that using RF sputter deposition of the ITO always leads to more efficient devices than ion beam sputter deposition. An important aspect of the former technique is the exposure of the single crystal p-InP substrates to a very low plasma power prior to deposition. Substrates treated in this manner have also been used for ion beam deposition of ITO. In this case the cells behave very similarly to the RF deposited cells, thus suggesting that the lower power plasma exposure (LPPE) is the crucial process step.

Coutts, T. J.↗

Advances in silicon carbide Chemical Vapor Deposition (CVD) for semiconductor device fabrication

Improved SiC chemical vapor deposition films of both 3C and 6H polytypes were grown on vicinal (0001) 6H-SiC wafers cut from single-crystal boules. These films were produced from silane and propane in hydrogen at one atmosphere at a temperature of 1725 K. Among the more important factors which affected the structure and morphology of the grown films were the tilt angle of the substrate, the polarity of the growth surface, and the pregrowth surface treatment of the substrate. With proper pregrowth surface treatment, 6H films were grown on 6H substrates with tilt angles as small as 0.1 degrees. In addition, 3C could be induced to grow within selected regions on a 6H substrate. The polarity of the substrate was a large factor in the incorporation of dopants during epitaxial growth. A new growth model is discussed which explains the control of SiC polytype in epitaxial growth on vicinal (0001) SiC substrates.

Powell, J. Anthony↗

Quantitative measurement of the "feel" of fabric

Device handle of fabric is a property related to flexibility, pliability, or compressibility. Technique requires extraction of flat circular sample of fabric through convergent nozzle.

Alley, V. L., Jr.↗

Silicon Solar Cell Fabrication Technology

Device fabrication and photoconductive lifetime decay measurements were used to characterize single and polycrystalline silicon substracts. The device characterization of the processed materials was done by spectral response measurements and absolute quantum efficiency at a single wavelength. The results were then reduced to yield the diffusion length of the various samples. The photoconductive lifetime decay method was implemented in order to determine the minority carrier lifetime in unprocessed wafers.

Stafsudd, O. M.↗

Method for fabricating semiconductor devices

A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term in situ herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed. An alternative embodiment of the present invention comprising an additional step, namely the termination of the gallium arsenide by a two monolayer thickness of epitaxial aluminum arsenide as a diffusion barrier, enables the recovery of Schottky barrier behavior, namely a rectified I-V characteristic. The present invention provides a significant breakthrough in the fabrication of III-V semiconductor devices wherein excellent Ohmic contact and Schottky barrier interfaces to such devices can be achieved simply and inexpensively and without requiring the high temperature processing of the prior art and also without requiring the use of exotic high temperature refractory materials as substitutes for those preferred contact metals such as gold, aluminum and the like.

Kaiser, William J.↗

Flexible thermal device

Fabrication of expansion joint, vibration isolator device with sufficient cross sectional area for high thermal conductivity is discussed. Device consists of multiple layers of metal foil which may be designed to meet specific applications. Thermodynamic properties of the device and illustration of construction are provided.

Wallace, S. D.↗

Templates for Fabricating Nanowire/Nanoconduit-Based Devices

An effort is underway to develop processes for making templates that could be used as deposition molds and etching masks in the fabrication of devices containing arrays of nanowires and/or nanoconduits. Highly-ordered, optical-fiber arrays consisting of dissimilar polymers comprise the template technology. The selective removal of the fiber cores in specific solvents creates the porous templates to be filled with a "top-down" deposition process such as electrochemical deposition, sputter deposition, molecular beam epitaxy, and the like. Typically, the fiber bundles consist of polystyrene (PS) fiber cores, which are clad with varying thickness poly(methyl methacrylate) (PMMA). When arranged in hexagonal, close-packed configuration and pulled, the fibers form highly-ordered arrays comprised of PS fiber cores surrounded by a continuous matrix of PMMA. The ratio of PMMA cladding thickness to PS core diameter determines the spacing between PS fiber cores and typically ranges from 3:1 to 1:1. Essentially, the simultaneous heating and drawing or pulling in the longitudinal direction of polymer-fiber arrays fuses the fibers together.

Sakamoto, Jeffrey↗

InP tunnel junction for InGaAs/InP tandem solar cells

Chemical beam epitaxy (CBE) has been shown to allow the growth of high quality materials with reproducible complex compositional and doping profiles. The main advantage of CBE compared to metalorganic chemical vapor deposition (MOCVD), the most popular technique for InP-based photovoltaic device fabrication, is the ability to grow high purity epilayers at much lower temperatures (450-530 C). We have previously shown that CBE is perfectly suited toward the fabrication of complex photovoltaic devices such as InP/InGaAs monolithically integrated tandem solar cells, because its low process temperature preserves the electrical characteristics of the InGaAs tunnel junction commonly used as an ohmic interconnect. In this work using CBE for the fabrication of optically transparent (with respect to the bottom cell) InP tunnel diodes is demonstrated. Epitaxial growth were performed in a Riber CBE 32 system using PH3 and TMIn as III and V precursors. Solid Be (p-type) and Si (n-type) have been used as doping sources, allowing doping levels up to 2 x 10(exp -19)/cu cm and 1 x 10(exp -19)/cu cm for n and p type respectively. The InP tunnel junction characteristics and the influence of the growth's conditions (temperature, growth rate) over its performance have been carefully investigated. InP p(++)/n(++) tunnel junction with peak current densities up to 1600 A/sq cm and maximum specific resistivities (V(sub p)/I(sub p) - peak voltage to peak current ratio) in the range of 10(exp -4) Omega-sq cm were obtained. The obtained peak current densities exceed the highest results previously reported for their lattice matched counterparts, In(0.53)Ga( 0.47)As and should allow the realization of improved minimal absorption losses in the interconnect InP/InGaAs tandem devices for Space applications. Owing to the low process temperature required for the top cell, these devices exhibit almost no degradation of its characteristics after the growth of subsequent thick InP layer suggesting minimal doping cross diffusion in the narrow space-charge region (approximately 1-5 nm) of the device. The fabrication of tandem devices using InP tunnel diodes as interconnect is in progress and will be reported at the conference.

Vilela, M. F.↗

Solid-state curved focal plane arrays

The present invention relates to curved focal plane arrays. More specifically, the present invention relates to a system and method for making solid-state curved focal plane arrays from standard and high-purity devices that may be matched to a given optical system. There are two ways to make a curved focal plane arrays starting with the fully fabricated device. One way, is to thin the device and conform it to a curvature. A second way, is to back-illuminate a thick device without making a thinned membrane. The thick device is a special class of devices; for example devices fabricated with high purity silicon. One surface of the device (the non VLSI fabricated surface, also referred to as the back surface) can be polished to form a curved surface.

Nikzad, Shouleh↗